mirror of https://github.com/YosysHQ/picorv32.git
293 lines
6.1 KiB
Verilog
293 lines
6.1 KiB
Verilog
`timescale 1 ns / 1 ps
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`ifndef VERILATOR
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module testbench #(
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parameter VERBOSE = 0
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);
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reg clk = 1;
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reg resetn = 1;
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wire trap;
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always #5 clk = ~clk;
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initial begin
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repeat (100) @(posedge clk);
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resetn <= 0;
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end
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initial begin
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if ($test$plusargs("vcd")) begin
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$dumpfile("testbench.vcd");
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$dumpvars(0, testbench);
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end
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repeat (1000000) @(posedge clk);
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$display("TIMEOUT");
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$finish;
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end
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wire trace_valid;
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wire [35:0] trace_data;
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integer trace_file;
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initial begin
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if ($test$plusargs("trace")) begin
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trace_file = $fopen("testbench.trace", "w");
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repeat (10) @(posedge clk);
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while (!trap) begin
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@(posedge clk);
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if (trace_valid)
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$fwrite(trace_file, "%x\n", trace_data);
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end
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$fclose(trace_file);
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$display("Finished writing testbench.trace.");
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end
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end
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picorv32_wrapper #(
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.VERBOSE (VERBOSE)
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) top (
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.wb_clk(clk),
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.wb_rst(resetn),
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.trap(trap),
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.trace_valid(trace_valid),
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.trace_data(trace_data)
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);
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endmodule
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`endif
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module picorv32_wrapper #(
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parameter BOOTROM_MEMFILE = "",
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parameter BOOTROM_MEMDEPTH = 16384 * 4,
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parameter VERBOSE = 0
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) (
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input wb_clk,
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input wb_rst,
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output trap,
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output trace_valid,
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output [35:0] trace_data
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);
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wire tests_passed;
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reg [31:0] irq;
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wire mem_instr;
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always @* begin
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irq = 0;
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irq[4] = &uut.picorv32_core.count_cycle[12:0];
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irq[5] = &uut.picorv32_core.count_cycle[15:0];
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end
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wire [31:0] wb_m2s_adr;
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wire [31:0] wb_m2s_dat;
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wire [3:0] wb_m2s_sel;
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wire wb_m2s_we;
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wire wb_m2s_cyc;
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wire wb_m2s_stb;
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wire [31:0] wb_s2m_dat;
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wire wb_s2m_ack;
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wb_ram #(
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.depth (16384 * 4),
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.VERBOSE (VERBOSE)
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) ram ( // Wishbone interface
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.wb_clk_i(wb_clk),
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.wb_rst_i(wb_rst),
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.wb_adr_i(wb_m2s_adr),
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.wb_dat_i(wb_m2s_dat),
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.wb_stb_i(wb_m2s_stb),
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.wb_cyc_i(wb_m2s_cyc),
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.wb_dat_o(wb_s2m_dat),
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.wb_ack_o(wb_s2m_ack),
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.wb_sel_i(wb_m2s_sel),
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.wb_we_i(wb_m2s_we),
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.mem_instr(mem_instr),
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.tests_passed(tests_passed)
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);
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picorv32_wb #(
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`ifndef SYNTH_TEST
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`ifdef SP_TEST
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.ENABLE_REGS_DUALPORT(0),
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`endif
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`ifdef COMPRESSED_ISA
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.COMPRESSED_ISA(1),
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`endif
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.ENABLE_MUL(1),
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.ENABLE_DIV(1),
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.ENABLE_IRQ(1),
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.ENABLE_TRACE(1)
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`endif
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) uut (
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.trap (trap),
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.irq (irq),
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.trace_valid (trace_valid),
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.trace_data (trace_data),
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.mem_instr(mem_instr),
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.wb_clk_i(wb_clk),
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.wb_rst_i(wb_rst),
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.wbm_adr_o(wb_m2s_adr),
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.wbm_dat_i(wb_s2m_dat),
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.wbm_stb_o(wb_m2s_stb),
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.wbm_ack_i(wb_s2m_ack),
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.wbm_cyc_o(wb_m2s_cyc),
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.wbm_dat_o(wb_m2s_dat),
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.wbm_we_o(wb_m2s_we),
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.wbm_sel_o(wb_m2s_sel)
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);
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reg [1023:0] firmware_file;
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initial begin
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if (!$value$plusargs("firmware=%s", firmware_file))
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firmware_file = "firmware/firmware.hex";
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$readmemh(firmware_file, ram.mem);
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end
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integer cycle_counter;
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always @(posedge wb_clk) begin
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cycle_counter <= !wb_rst ? cycle_counter + 1 : 0;
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if (!wb_rst && trap) begin
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`ifndef VERILATOR
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repeat (10) @(posedge wb_clk);
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`endif
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$display("TRAP after %1d clock cycles", cycle_counter);
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if (tests_passed) begin
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$display("ALL TESTS PASSED.");
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$finish;
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end else begin
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$display("ERROR!");
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if ($test$plusargs("noerror"))
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$finish;
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$stop;
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end
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end
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end
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endmodule
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/* ISC License
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*
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* Verilog on-chip RAM with Wishbone interface
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*
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* Copyright (C) 2014, 2016 Olof Kindgren <olof.kindgren@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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module wb_ram #(
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parameter depth = 256,
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parameter memfile = "",
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parameter VERBOSE = 0
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) (
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input wb_clk_i,
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input wb_rst_i,
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input [31:0] wb_adr_i,
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input [31:0] wb_dat_i,
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input [3:0] wb_sel_i,
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input wb_we_i,
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input wb_cyc_i,
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input wb_stb_i,
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output reg wb_ack_o,
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output reg [31:0] wb_dat_o,
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input mem_instr,
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output reg tests_passed
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);
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reg verbose;
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initial verbose = $test$plusargs("verbose") || VERBOSE;
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initial tests_passed = 0;
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reg [31:0] adr_r;
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wire valid = wb_cyc_i & wb_stb_i;
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always @(posedge wb_clk_i) begin
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adr_r <= wb_adr_i;
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// Ack generation
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wb_ack_o <= valid & !wb_ack_o;
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if (wb_rst_i)
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begin
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adr_r <= {32{1'b0}};
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wb_ack_o <= 1'b0;
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end
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end
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wire ram_we = wb_we_i & valid & wb_ack_o;
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wire [31:0] waddr = adr_r[31:2];
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wire [31:0] raddr = wb_adr_i[31:2];
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wire [3:0] we = {4{ram_we}} & wb_sel_i;
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wire [$clog2(depth/4)-1:0] raddr2 = raddr[$clog2(depth/4)-1:0];
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wire [$clog2(depth/4)-1:0] waddr2 = waddr[$clog2(depth/4)-1:0];
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reg [31:0] mem [0:depth/4-1] /* verilator public */;
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always @(posedge wb_clk_i) begin
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if (ram_we) begin
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if (verbose)
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$display("WR: ADDR=%08x DATA=%08x STRB=%04b",
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adr_r, wb_dat_i, we);
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if (adr_r[31:0] == 32'h1000_0000)
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if (verbose) begin
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if (32 <= wb_dat_i[7:0] && wb_dat_i[7:0] < 128)
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$display("OUT: '%c'", wb_dat_i[7:0]);
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else
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$display("OUT: %3d", wb_dat_i[7:0]);
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end else begin
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$write("%c", wb_dat_i[7:0]);
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`ifndef VERILATOR
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$fflush();
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`endif
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end
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else
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if (adr_r[31:0] == 32'h2000_0000)
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if (wb_dat_i[31:0] == 123456789)
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tests_passed = 1;
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end
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end
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always @(posedge wb_clk_i) begin
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if (waddr2 < 64 * 1024 / 4) begin
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if (we[0])
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mem[waddr2][7:0] <= wb_dat_i[7:0];
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if (we[1])
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mem[waddr2][15:8] <= wb_dat_i[15:8];
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if (we[2])
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mem[waddr2][23:16] <= wb_dat_i[23:16];
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if (we[3])
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mem[waddr2][31:24] <= wb_dat_i[31:24];
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end
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if (valid & wb_ack_o & !ram_we)
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if (verbose)
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$display("RD: ADDR=%08x DATA=%08x%s", adr_r, mem[raddr2], mem_instr ? " INSN" : "");
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wb_dat_o <= mem[raddr2];
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end
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initial begin
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if (memfile != "")
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$readmemh(memfile, mem);
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end
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endmodule
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