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12274e9f8a
The core file specifies targets for FPGA implementation (fusesoc build hx8kdemo) and simulation (fusesoc run --tool=<tool> --target=sim hx8kdemo --firmware=path/to/firmware.he). Simulation has been tested successfully with icarus, modelsim and xsim
35 lines
657 B
Text
35 lines
657 B
Text
CAPI=2:
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name : ::hx8kdemo:0
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filesets:
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hx8kdemo:
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files: [hx8kdemo.v]
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file_type : verilogSource
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depend : [picosoc]
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hx8ksim:
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files:
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- hx8kdemo_tb.v
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file_type : verilogSource
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depend : [spiflash, "yosys:techlibs:ice40"]
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constraints:
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files: [hx8kdemo.pcf]
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file_type : PCF
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targets:
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synth:
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default_tool : icestorm
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filesets : [constraints, hx8kdemo]
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tools:
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icestorm:
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arachne_pnr_options : [-d, 8k]
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toplevel : [hx8kdemo]
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sim:
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default_tool : icarus
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filesets : [hx8kdemo, hx8ksim]
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tools:
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xsim:
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xelab_options : [--timescale, 1ns/1ps]
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toplevel : [testbench]
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