Programming the Nexys 4 DDR Artix 7 FPGA Trainer Board

Dmitrii edited this page 2019-06-03 09:11:56 -04:00

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4 Commits

Author	SHA1	Message	Date
Dmitrii	9176f3fee2	Fix xcd->xdc typo, add tcl directory hint	2019-06-03 09:11:56 -04:00
Emilio Rojas	c2867abe6b	remove links, indicate which is the generated file	2018-10-10 13:31:55 -06:00
Emilio Rojas	c28ff9b717	Updated Programming the Nexys 4 DDR Artix 7 FPGA Trainer Board (markdown)	2018-10-10 13:28:23 -06:00
Emilio Rojas	0781716a9e	Add instructions for nexys 4 ddr board	2018-10-10 13:26:48 -06:00