remove links, indicate which is the generated file

Emilio Rojas 2018-10-10 13:31:55 -06:00
parent c28ff9b717
commit c2867abe6b
1 changed files with 5 additions and 3 deletions

@ -4,7 +4,7 @@ First of all you will need Vivado, follow the instructions at https://reference.
Then you will need to update two files in order to synthesize, implement and generate the bitstream. Then you will need to update two files in order to synthesize, implement and generate the bitstream.
First update [scripts/vivado/synth_system.tcl](scripts/vivado/synth_system.tcl). Change the following line: First update ```scripts/vivado/synth_system.tcl```. Change the following line:
``` ```
synth_design -part xc7k70t-fbg676 -top system synth_design -part xc7k70t-fbg676 -top system
@ -15,7 +15,7 @@ synth_design -part xc7a100tcsg324-1 -top system
``` ```
in order to update the target device to the FPGA in the Nexys 4 DDR board. in order to update the target device to the FPGA in the Nexys 4 DDR board.
Then update [scripts/vivado/synth_system.xcd](scripts/vivado/synth_system.xcd). Use Then update ```scripts/vivado/synth_system.xcd```. Use
``` ```
# XDC File for Nexys 4 DDR Board # XDC File for Nexys 4 DDR Board
@ -53,4 +53,6 @@ set_property IOSTANDARD LVCMOS33 [get_ports {out_byte_en}]
``` ```
Note this is basically the same file, what has changed are a few ports that in the xc7a100tcsg324-1 device are disabled(reserved for ground pins or nonexistent), you might want to rearrange the pins. Note this is basically the same file, what has changed are a few ports that in the xc7a100tcsg324-1 device are disabled(reserved for ground pins or nonexistent), you might want to rearrange the pins.
Now in vivado go to Tools>Run Tcl Script..., make sure the Tcl Console working directory is in [scripts/vivado](scripts/vivado). Now in vivado go to Tools>Run Tcl Script..., make sure the Tcl Console working directory is in ```scripts/vivado```.
A file ```scripts/vivado/synth_system.bit``` should have been created, use this to program your device.