upsilon/firmware/rtl/testbench.hpp

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#pragma once
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#include <verilated.h>
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#include "util.hpp"
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/* https://zipcpu.com/blog/2017/06/21/looking-at-verilator.html */
template <class TOP> class TB {
int tick_count;
int bailout;
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public:
TOP mod;
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TB(int argc, char *argv[], int _bailout = 0) : mod(), bailout(_bailout) {
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mod.clk = 0;
tick_count = 0;
}
virtual ~TB() {
mod.final();
}
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virtual void posedge() {}
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void run_clock() {
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mod.clk = !mod.clk;
mod.eval();
Verilated::timeInc(1);
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posedge();
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mod.clk = !mod.clk;
mod.eval();
Verilated::timeInc(1);
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tick_count++;
if (bailout > 0 && tick_count >= bailout)
exit(1);
if (Verilated::gotError())
exit(1);
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}
};