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upsilon/gateware/csr2mp.py

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Python
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csr to micropython
2023-06-21 18:47:52 -04:00
#!/usr/bin/python3
# Copyright 2023 (C) Peter McGoron
#
# This file is a part of Upsilon, a free and open source software project.
# For license terms, refer to the files in `doc/copying` in the Upsilon
# source distribution.
#######################################################################
#
Progress on PicoRV32 1) The PicoRV32 bus was not generated correctly. Running "finalize" on the bus, which is what the SoC does, does not generate the bus logic correctly. I don't know if this is a bug or if the SoC bus generator is only meant to be used in the main SoC. Currently the bus logic is copied from the LiteX finalize code. 2) Add test micropython code to load code. 3) Removed BRAM. The Wishbone cache was messing with the direct implementation of the BRAM because the BRAM did not implement all the bus features correctly. LiteX has a Wishbone "SRAM" module, and despite it's name it can also generate BRAM if there are available BRAM. This is how the ROM and the startup RAM are implemented. The PicoRV32 ram is now using this SRAM.
2024-02-20 10:28:51 -05:00
# This file generates memory locations
csr to micropython
2023-06-21 18:47:52 -04:00
#
# TODO: Devicetree?
refactor csr2mp and docker Makefile
2023-06-26 15:49:20 -04:00
import collections
zero scan and documentation
2023-06-23 18:15:53 -04:00
import argparse
csr to micropython
2023-06-21 18:47:52 -04:00
import json
import sys
refactor compiles
2023-06-28 18:49:26 -04:00
import mmio_descr
zero scan and documentation
2023-06-23 18:15:53 -04:00
Progress on PicoRV32 1) The PicoRV32 bus was not generated correctly. Running "finalize" on the bus, which is what the SoC does, does not generate the bus logic correctly. I don't know if this is a bug or if the SoC bus generator is only meant to be used in the main SoC. Currently the bus logic is copied from the LiteX finalize code. 2) Add test micropython code to load code. 3) Removed BRAM. The Wishbone cache was messing with the direct implementation of the BRAM because the BRAM did not implement all the bus features correctly. LiteX has a Wishbone "SRAM" module, and despite it's name it can also generate BRAM if there are available BRAM. This is how the ROM and the startup RAM are implemented. The PicoRV32 ram is now using this SRAM.
2024-02-20 10:28:51 -05:00
with open(sys.argv[1], 'rt') as f:
j = json.load(f)
zero scan and documentation
2023-06-23 18:15:53 -04:00
Progress on PicoRV32 1) The PicoRV32 bus was not generated correctly. Running "finalize" on the bus, which is what the SoC does, does not generate the bus logic correctly. I don't know if this is a bug or if the SoC bus generator is only meant to be used in the main SoC. Currently the bus logic is copied from the LiteX finalize code. 2) Add test micropython code to load code. 3) Removed BRAM. The Wishbone cache was messing with the direct implementation of the BRAM because the BRAM did not implement all the bus features correctly. LiteX has a Wishbone "SRAM" module, and despite it's name it can also generate BRAM if there are available BRAM. This is how the ROM and the startup RAM are implemented. The PicoRV32 ram is now using this SRAM.
2024-02-20 10:28:51 -05:00
print("from micropython import const")
csr to micropython
2023-06-21 18:47:52 -04:00
Progress on PicoRV32 1) The PicoRV32 bus was not generated correctly. Running "finalize" on the bus, which is what the SoC does, does not generate the bus logic correctly. I don't know if this is a bug or if the SoC bus generator is only meant to be used in the main SoC. Currently the bus logic is copied from the LiteX finalize code. 2) Add test micropython code to load code. 3) Removed BRAM. The Wishbone cache was messing with the direct implementation of the BRAM because the BRAM did not implement all the bus features correctly. LiteX has a Wishbone "SRAM" module, and despite it's name it can also generate BRAM if there are available BRAM. This is how the ROM and the startup RAM are implemented. The PicoRV32 ram is now using this SRAM.
2024-02-20 10:28:51 -05:00
for key in j["csr_registers"]:
picorv32 now runs: debugging outputs
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if key.startswith("pico0"):
Progress on PicoRV32 1) The PicoRV32 bus was not generated correctly. Running "finalize" on the bus, which is what the SoC does, does not generate the bus logic correctly. I don't know if this is a bug or if the SoC bus generator is only meant to be used in the main SoC. Currently the bus logic is copied from the LiteX finalize code. 2) Add test micropython code to load code. 3) Removed BRAM. The Wishbone cache was messing with the direct implementation of the BRAM because the BRAM did not implement all the bus features correctly. LiteX has a Wishbone "SRAM" module, and despite it's name it can also generate BRAM if there are available BRAM. This is how the ROM and the startup RAM are implemented. The PicoRV32 ram is now using this SRAM.
2024-02-20 10:28:51 -05:00
print(f'{key} = const({j["csr_registers"][key]["addr"]})')
csr to micropython
2023-06-21 18:47:52 -04:00
picorv32 now runs: debugging outputs
2024-02-21 23:58:59 -05:00
print(f'pico0_ram = const({j["memories"]["pico0_ram"]["base"]})')
Get PicoRV32 to execute code 1. Update LiteX to 2023.12. This update adds wishbone bus addressing modes. Before this update, all wishbone buses used word addressing. For example, 0x0 mapped to word 0, 0x0 mapped to word 1, etc. This caused problems with the PicoRV32 and other modules, which are byte addressed. 2. Use adapter to convert between byte and word addressing. The SRAM is word addressed. The PicoRV32 shifts the address down by two bits to address the correct word. The PicoRV32 core seems to expect this. 3. Add debug register output. This is not working yet. 4. Use LiteX PicoRV32 wishbone adapter instead of PicoRV32 default. This seems to be simpler (combinatorial not synchronous). 5. Add some documentation. 6. Seperate config to new config file.
2024-02-25 13:58:34 -05:00
print(f'pico0_dbg_reg = const({j["memories"]["pico0_dbg_reg"]["base"]})')