39 lines
1.5 KiB
ReStructuredText
39 lines
1.5 KiB
ReStructuredText
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Copyright 2024 (C) Peter McGoron.
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This file is a part of Upsilon, a free and open source software project.
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For license terms, refer to the files in ``doc/copying`` in the Upsilon
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source distribution.
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***************************************************
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====================
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System Within a Chip
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====================
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A *system within a chip* (SWiC) is a SoC within a SoC. Upsilon has the
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capability to add SWiCs that can be controlled by the main CPU. The CPU for
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the SWiC is the PicoRV32, which is a RISC-V RVI32 core with optional C, M
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extensions and custom-made non-branching instructions.
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----------------
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Main CPU Control
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----------------
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The main CPU controls the SWiC using two methods:
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1. LiteX CSR Registers. This is for simple things where the main CPU should
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have 100% control at all times, like starting and stopping the CPU.
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2. *Preemptive interfaces* (PI), which sit in front of a Wishbone slave. The
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main CPU has a LiteX CSR register which selects the Wishbone master the
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Wishbone slave connects to.
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In usual operation the SWiC RAM sits behind a PI. Before the SWiC starts, the
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main CPU switches the PI to itself, fills the RAM with the program, and then
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switches it back to the SWiC. When the SWiC starts, the SWiC has read-write
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access to the RAM. PIs are also used for connecting to external IO (like SPI).
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In the future, there will be master-read-slave-write interfaces to transfer
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bulk memory from the SWiC to the main CPU (for instances, raster scanning).
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See /gateware/soc.py for implementation notes.
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