upsilon/firmware/rtl/spi/spi_switch.v

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/* This module is a co-operative crossbar for the wires only. Each end
* implements its own SPI master.
*
* This crossbar is entirely controlled by the kernel.
*/
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module spi_switch #(
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parameter PORTS = 3
) (
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/* verilator lint_off UNUSEDSIGNAL */
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input [PORTS-1:0] select,
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/* verilator lint_on UNUSEDSIGNAL */
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output reg mosi,
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input miso,
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output reg sck,
output reg ss_L,
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input [PORTS-1:0] mosi_ports,
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output reg [PORTS-1:0] miso_ports,
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input [PORTS-1:0] sck_ports,
input [PORTS-1:0] ss_L_ports
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);
/* Avoid using for loops, they might not synthesize correctly.
Do things the old, dumb way instead.
*/
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`define do_select(n) \
mosi = mosi_ports[n]; \
miso_ports = {{(PORTS-1){1'b0}},miso} << n; \
sck = sck_ports[n]; \
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ss_L = ss_L_ports[n]
`define check_select(n) \
if (select[n]) begin \
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`do_select(n); \
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end
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generate if (PORTS == 3) always @(*) begin
`check_select(2)
else `check_select(1)
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else begin
`do_select(0);
end
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end else always @(*) begin
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`check_select(1)
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else begin
`do_select(0);
end
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end endgenerate
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endmodule
`undefineall