move autoapproach to possibly useful waveform module: not yet tested
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05f8878751
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89938a2ff6
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@ -1,125 +0,0 @@
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#include <random>
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#include <cmath>
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#include "Vautoapproach_sim.h"
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#include "../testbench.hpp"
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/* TODO: generalize so bram_interface_sim can use it.
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* This should make a triangle wave.
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*/
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class RefreshModule {
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uint32_t *store_32;
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size_t word_amnt;
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bool pending_refresh_start;
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public:
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void posedge(uint8_t &refresh_start, uint32_t &start_addr,
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uint8_t refresh_finished) {
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if (refresh_start && refresh_finished) {
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refresh_start = 0;
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} else if (pending_refresh_start && !refresh_start) {
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pending_refresh_start = false;
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refresh_start = 1;
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}
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}
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RefreshModule(size_t _word_amnt, size_t _start_addr)
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: word_amnt{_word_amnt}
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, start_addr{_start_addr} {
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store_32 = new uint32_t[_start_addr];
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for (size_t i = 0; i < start_addr; i++) {
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/* 0xFFFFF is the maximum DAC value */
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store_32[i] = 0xFFFFF*max(double)i/start_addr;
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}
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pending_refresh_start = true;
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}
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~RefreshModule() {
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delete[] store_32;
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}
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};
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/* TODO: make generic SPI delay class because this code has been duplicated
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* many times over now. This function is also similar to the control loop
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* ADC simulation. */
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class GaussianZPiezo {
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std::default_random_engine generator;
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std::normal_distribution<> dist;
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double scale;
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double setpt;
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double midpt;
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double stretch;
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double sample() {return scale*dist(generator);}
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GaussianZPiezo(double scale, double mean, double dev, double setpt,
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double midpt, double stretch, int seed,
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uint16_t dac_wait_count,
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uint16_t adc_wait_count)
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: scale{scale}, dist{mean,dev}, generator{},
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, setpt{setpt}, midpt{midpt}, stretch{stretch},
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, dac_wait_count_max{dac_wait_count}
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, adc_wait_count_max{adc_wait_count} {
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if (seed < 0) {
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std::random_device rd;
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generator.seed(rd());
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} else {
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generator.seed(seed);
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}
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}
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/* Sigmoid function. This function is
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c(x-d)
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f(x) = A*-------------------
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sqrt(1+(c(x-d))^2)
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where A is the setpoint and c is how compressed the sigmoid is.
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*/
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double f(uint32_t x) {
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double x_shift = x - midpt + sample();
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return setpt*stretch*x_shift/sqrt(fma(x_shift,x_shift,1));
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}
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public:
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void posedge(uint8_t &dac_finished, uint8_t dac_arm,
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uint32_t dac_out,
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uint8_t &adc_finished, uint8_t adc_arm,
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uint32_t &adc_out) {
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if (adc_arm && adc_wait_counter == adc_wait_counter_max &&
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!adc_finished) {
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adc_finished = 1;
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adc_out = sample();
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} else if (!adc_arm) {
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adc_finished = 0;
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adc_wait_counter = 0;
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} else {
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adc_wait_counter++;
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}
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if (dac_arm && dac_wait_counter == dac_wait_counter_max &&
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!dac_finished) {
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dac_finished = 1;
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}
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};
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class AA_TB : TB<Vautoapproach_sim> {
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RefreshModule refresh;
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GaussianZPiezo piezo;
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void posedge() override;
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AA_TB(size_t word_amnt, uint32_t start_addr)
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: refresh{word_amnt, start_addr} {}
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~AA_TB() {}
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};
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AA_TB::posedge() {
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refresh.posedge(mod.refresh_start, mod.start_addr,
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mod.refresh_finished);
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}
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int main(int argc, char **argv) {
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return 0;
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}
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@ -1,96 +0,0 @@
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module autoapproach_sim #(
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parameter DAC_WID = 24,
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parameter DAC_DATA_WID = 20,
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parameter ADC_WID = 24,
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parameter TIMER_WID = 32,
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parameter WORD_WID = 24,
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parameter WORD_AMNT_WID = 11,
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parameter [WORD_AMNT_WID-1:0] WORD_AMNT = 2047,
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parameter RAM_WID = 32,
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parameter RAM_WORD_WID = 16,
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parameter RAM_WORD_INCR = 2,
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parameter TOTAL_RAM_WORD_MINUS_ONE = 4095
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) (
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input clk,
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input arm,
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output stopped,
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output detected,
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input polarity,
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input [ADC_WID-1:0] setpoint,
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input [TIMER_WID-1:0] time_to_wait,
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/* User interface */
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input refresh_start,
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input [RAM_WID-1:0] start_addr,
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output refresh_finished,
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/* DAC wires. */
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input dac_finished,
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output dac_arm,
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output [DAC_WID-1:0] dac_out,
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input adc_finished,
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output adc_arm,
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input [ADC_WID-1:0] measurement
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input[RAM_WORD_WID-1:0] backing_store [TOTAL_RAM_WORD_MINUS_ONE:0]
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);
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wire [RAM_WID-1:0] ram_dma_addr;
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wire [RAM_WORD_WID-1:0] ram_word;
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wire ram_read;
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wire ram_valid;
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dma_sim #(
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.RAM_WID(RAM_WID),
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.RAM_WORD_WID(RAM_WORD_WID),
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.RAM_REAL_START(RAM_REAL_START),
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.RAM_CNTR_LEN(RAM_CNTR_LEN),
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.TOTAL_RAM_WORD_MINUS_ONE(TOTAL_RAM_WORD_MINUS_ONE),
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.DELAY_CNTR_LEN(DELAY_CNTR_LEN),
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.DELAY_TOTAL(DELAY_TOTAL)
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) dma_sim (
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.clk(clk),
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.ram_dma_addr(ram_dma_addr),
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.ram_word(ram_word),
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.ram_read(ram_read),
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.ram_valid(ram_valid),
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.backing_store(backing_store)
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);
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autoapproach #(
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.DAC_WID(DAC_WID),
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.DAC_DATA_WID(DAC_DATA_WID),
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.ADC_WID(ADC_WID),
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.TIMER_WID(TIMER_WID),
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.WORD_WID(WORD_WID),
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.WORD_AMNT_WID(WORD_AMNT_WID),
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.WORD_AMNT(WORD_AMNT),
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.RAM_WID(RAM_WID),
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.RAM_WORD_WID(RAM_WORD_WID),
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.RAM_WORD_INCR(RAM_WORD_INCR)
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) aa (
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.clk(clk),
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.arm(arm),
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.stopped(stopped),
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.detected(detected),
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.polarity(polarity),
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.setpoint(setpoint),
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.time_to_wait(time_to_wait),
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.refresh_start(refresh_start),
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.start_addr(start_addr),
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.refresh_finished(refresh_finished),
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.ram_dma_addr(ram_dma_addr),
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.ram_word(ram_word),
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.ram_read(ram_read),
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.ram_valid(ram_valid),
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.dac_finished(dac_finished),
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.dac_arm(dac_arm),
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.dac_out(dac_out),
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.adc_finished(adc_finished),
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.adc_arm(adc_arm),
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.measurement(measurement)
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);
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endmodule
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@ -4,7 +4,7 @@
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* This crossbar is entirely controlled by the kernel.
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*/
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module spi_crossbar #(
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parameter PORTS = 2,
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parameter PORTS = 8,
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(
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input select[PORTS-1:0],
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@ -23,19 +23,27 @@ module spi_crossbar #(
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Do things the old, dumb way instead.
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*/
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always @(*) begin
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if (select[1]) begin
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mosi = mosi_ports[1];
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miso = miso_ports[1];
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sck = sck_ports[1];
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ss = ss_ports[1];
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end else begin
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/* Select zeroth slot by default. No latches. */
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mosi = mosi_ports[0];
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miso = miso_ports[0];
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sck = sck_ports[0];
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ss = ss_ports[0];
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`define do_select(n) \
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mosi = mosi_ports[n]; \
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miso = miso_ports[n]; \
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sck = sck_ports[n]; \
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ss = ss_ports[n]
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`define check_select(n) \
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if (select[n]) begin \
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do_select(n); \
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end
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always @(*) begin
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check_select(7)
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else check_select(6)
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else check_select(5)
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else check_select(4)
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else check_select(3)
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else check_select(2)
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else check_select(1)
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else do_select(0)
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end
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endmodule
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`undefineall
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@ -1,12 +1,13 @@
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/* Autoapproach module. This module applies a waveform located in memory
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* (and copied into Block RAM). This waveform is arbitrary but of fixed
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* length.
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* time in between sent sample, total period 10-50ms
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*/
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module autoapproach #(
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/* Write a waveform to a DAC. */
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module waveform #(
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parameter DAC_WID = 24,
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parameter DAC_DATA_WID = 20,
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parameter ADC_WID = 24,
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parameter DAC_WID_SIZ = 5,
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parameter DAC_POLARITY = 0,
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parameter DAC_PHASE = 1,
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parameter DAC_CYCLE_HALF_WAIT = 10,
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parameter DAC_CYCLE_HALF_WAIT_SIZ = 4,
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parameter DAC_SS_WAIT = 5,
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parameter DAC_SS_WAIT_SIZ = 3,
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parameter TIMER_WID = 32,
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parameter WORD_WID = 24,
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parameter WORD_AMNT_WID = 11,
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@ -17,11 +18,6 @@ module autoapproach #(
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) (
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input clk,
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input arm,
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output stopped,
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output detected,
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input polarity,
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input [ADC_WID-1:0] setpoint,
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input [TIMER_WID-1:0] time_to_wait,
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/* User interface */
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@ -36,15 +32,18 @@ module autoapproach #(
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input ram_valid,
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/* DAC wires. */
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input dac_finished,
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output dac_arm,
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output [DAC_WID-1:0] dac_out,
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input adc_finished,
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output adc_arm,
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input [ADC_WID-1:0] measurement
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input miso,
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output mosi,
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input sck,
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output ss_L
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);
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wire [WORD_WID-1:0] word;
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reg word_next;
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wire word_ok;
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wire word_last;
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wire word_rst;
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bram_interface #(
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.WORD_WID(WORD_WID),
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.WORD_AMNT_WID(WORD_AMNT_WID),
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@ -59,22 +58,46 @@ bram_interface #(
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.word_last(word_last),
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.word_ok(word_ok),
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.word_rst(word_rst),
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.refresh_start(refresh_start),
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.start_addr(start_addr),
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.refresh_finished(refresh_finished),
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.ram_dma_addr(ram_dma_addr),
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.ram_word(ram_word),
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.ram_read(ram_read),
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.ram_valid(ram_valid)
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);
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wire dac_finished;
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reg dac_arm;
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reg [DAC_WID-1:0] dac_out;
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spi_master_ss_no_read #(
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.WID(DAC_WID),
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.WID_LEN(DAC_WID_SIZ),
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.CYCLE_HALF_WAIT(DAC_CYCLE_HALF_WAIT),
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.TIMER_LEN(DAC_CYCLE_HALF_WAIT_SIZ),
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.POLARITY(DAC_POLARITY),
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.PHASE(DAC_PHASE),
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.SS_WAIT(DAC_SS_WAIT),
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.SS_WAIT_TIMER_LEN(DAC_SS_WAIT_SIZ)
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) dac_master (
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.clk(clk),
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.mosi(mosi),
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.miso(miso),
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.sck_wire(sck),
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.ss_L(ss_L),
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.finished(dac_finished),
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.arm(dac_arm),
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.to_slave(dac_out)
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);
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localparam WAIT_ON_ARM = 0;
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localparam DO_WAIT = 1;
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localparam RECV_WORD = 2;
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localparam WAIT_ON_DAC = 3;
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localparam WAIT_ON_DETECTION = 4;
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localparam DETECTED = 5;
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reg [2:0] state = WAIT_ON_ARM;
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reg [1:0] state = WAIT_ON_ARM;
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reg [TIMER_WID-1:0] wait_timer = 0;
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@ -107,23 +130,10 @@ WAIT_ON_DAC: if (dac_finished) begin
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dac_arm <= 0;
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/* Was the last word read *the* last word? */
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if (word_last) begin
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state <= WAIT_ON_DETECTION;
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adc_arm <= 1;
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end else begin
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state <= WAIT_ON_ARM;
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end else begin
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state <= DO_WAIT;
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end
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endcase
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WAIT_ON_DETECTION: if (adc_finished) begin
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if ((polarity && measurement >= setpt) ||
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(!polarity && measurement <= setpt)) begin
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state <= DETECTED;
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detected <= 1;
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end
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end
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DETECTED: if (!arm) begin
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state <= WAIT_ON_ARM;
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detected <= 0;
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end
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endcase
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endmodule
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