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add yosys synth test for control loop

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Peter McGoron 2023-03-20 13:57:42 -04:00
parent 93c92b9f55
commit 0259523d20
1 changed files with 1 additions and 0 deletions
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firmware/rtl/control_loop/yosys_test.sh Normal file
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yosys -p "plugin -i systemverilog" -p "read_systemverilog control_loop.v control_loop_math.v ../spi/spi_master_ss_no_write.v ../spi/spi_master_ss.v boothmul.v intsat.v ../spi/spi_master.v ../spi/spi_master_no_write.v" -p "synth_xilinx"