Progress on PicoRV32
1) The PicoRV32 bus was not generated correctly. Running "finalize" on the bus, which is what the SoC does, does not generate the bus logic correctly. I don't know if this is a bug or if the SoC bus generator is only meant to be used in the main SoC. Currently the bus logic is copied from the LiteX finalize code. 2) Add test micropython code to load code. 3) Removed BRAM. The Wishbone cache was messing with the direct implementation of the BRAM because the BRAM did not implement all the bus features correctly. LiteX has a Wishbone "SRAM" module, and despite it's name it can also generate BRAM if there are available BRAM. This is how the ROM and the startup RAM are implemented. The PicoRV32 ram is now using this SRAM.
This commit is contained in:
parent
0cfa172a89
commit
06cf8807c3
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@ -45,11 +45,12 @@ hardware-execute:
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hardware-shell:
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docker exec -ti upsilon-hardware /bin/bash -l
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hardware-get:
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docker cp upsilon-hardware:/home/user/upsilon/gateware/build/digilent_arty/gateware/digilent_arty.v ../boot/
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docker cp upsilon-hardware:/home/user/upsilon/gateware/build/digilent_arty/gateware/digilent_arty.bit ../boot/
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docker cp upsilon-hardware:/home/user/upsilon/gateware/arty.dtb ../boot/
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# docker cp upsilon-hardware:/home/user/upsilon/gateware/mmio.py ../boot/
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docker cp upsilon-hardware:/home/user/upsilon/gateware/csr.json ../boot/
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# docker cp upsilon-hardware:/home/user/upsilon/gateware/picorv32.json ../boot/
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docker cp upsilon-hardware:/home/user/upsilon/gateware/picorv32.json ../boot/
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docker cp upsilon-hardware:/home/user/upsilon/gateware/mmio.py ../boot/
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hardware-clean:
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-docker container stop upsilon-hardware
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-docker container rm upsilon-hardware
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@ -42,3 +42,10 @@ automatically copied to `boot/mmio.py`).
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`comm` contains higher level wrappers for DAC and ADC pins. This module is
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documented well enough that you should be able to read it and understand
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how to use it.
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# FAQ
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## SCP Is Not Working
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SCP by default uses SFTP, which dropbear does not support. Pass `-O` to all
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SCP invocations to use the legacy SCP protocol.
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@ -8,12 +8,15 @@
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DEVICETREE_GEN_DIR=.
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all: build/digilent_arty/digilent_arty.bit arty.dtb
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all: build/digilent_arty/digilent_arty.bit arty.dtb mmio.py
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csr.json build/digilent_arty/digilent_arty.bit: soc.py
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cd rtl && make
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python3 soc.py
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mmio.py: csr.json csr2mp.py
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python3 csr2mp.py csr.json > mmio.py
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clean:
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rm -rf build csr.json arty.dts arty.dtb mmio.py
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@ -6,8 +6,7 @@
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# source distribution.
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#######################################################################
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#
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# This file generates a Micropython module "mmio" with functions that
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# do raw reads and writes to MMIO registers.
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# This file generates memory locations
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#
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# TODO: Devicetree?
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@ -17,163 +16,13 @@ import json
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import sys
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import mmio_descr
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class CSRHandler:
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"""
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Class that wraps the CSR file and fills in registers with information
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from those files.
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"""
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def __init__(self, csrjson, registers):
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"""
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Reads in the CSR files.
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with open(sys.argv[1], 'rt') as f:
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j = json.load(f)
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:param csrjson: Filename of a LiteX "csr.json" file.
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:param registers: A list of ``mmio_descr`` ``Descr``s.
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:param outf: Output file.
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"""
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self.registers = registers
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self.csrs = json.load(open(csrjson))
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print("from micropython import const")
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def update_reg(self, reg):
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"""
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Fill in size information from bitwidth json file.
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for key in j["csr_registers"]:
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if key.startswith("picorv32"):
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print(f'{key} = const({j["csr_registers"][key]["addr"]})')
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:param reg: The register.
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:raises Exception: When the bit width exceeds 64.
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"""
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regsize = None
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b = reg.blen
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if b <= 8:
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regsize = 8
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elif b <= 16:
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regsize = 16
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elif b <= 32:
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regsize = 32
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elif b <= 64:
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regsize = 64
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else:
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raise Exception(f"unsupported width {b} in {reg.name}")
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setattr(reg, "regsize", regsize)
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def get_reg_addr(self, reg, num=None):
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"""
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Get address of register.
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:param reg: The register.
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:param num: Select which register number. Registers without
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numerical suffixes require ``None``.
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:return: The address.
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"""
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if num is None:
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regname = f"base_{reg.name}"
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else:
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regname = f"base_{reg.name}_{num}"
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return self.csrs["csr_registers"][regname]["addr"]
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class InterfaceGenerator:
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"""
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Interface for file generation. Implement the unimplemented functions
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to generate a CSR interface for another language.
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"""
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def __init__(self, csr, outf):
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"""
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:param CSRHandler csr:
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:param FileIO outf:
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"""
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self.outf = outf
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self.csr = csr
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def print(self, *args):
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"""
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Print to the file specified in the initializer and without
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newlines.
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"""
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print(*args, end='', file=self.outf)
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def fun(self, reg, optype):
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""" Print function for reads/writes to register. """
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pass
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def header(self):
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""" Print header of file. """
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pass
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def print_file(self):
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self.print(self.header())
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for r in self.csr.registers:
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self.print(self.fun(r, "read"))
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if not r.rwperm != "read-only":
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self.print(self.fun(r, "write"))
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class MicropythonGenerator(InterfaceGenerator):
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def __init__(self, *args, **kwargs):
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super().__init__(*args, **kwargs)
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def get_accessor(self, reg, num):
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addr = self.csr.get_reg_addr(reg, num)
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if reg.regsize in [8, 16, 32]:
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return [f"machine.mem{reg.regsize}[{addr}]"]
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return [f"machine.mem32[{addr + 4}]", f"machine.mem32[{addr}]"]
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def print_write_register(self, indent, varname, reg, num):
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acc = self.get_accessor(reg, num)
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if len(acc) == 1:
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return f'{indent}{acc[0]} = {varname}\n'
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else:
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assert len(acc) == 2
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# Little Endian. See linux kernel, include/linux/litex.h
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return f'{indent}{acc[1]} = {varname} & 0xFFFFFFFF\n' + \
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f'{indent}{acc[0]} = {varname} >> 32\n'
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def print_read_register(self, indent, varname, reg, num):
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acc = self.get_accessor(reg, num)
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if len(acc) == 1:
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return f'{indent}return {acc[0]}\n'
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else:
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assert len(acc) == 2
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return f'{indent}return {acc[0]} | ({acc[1]} << 32)\n'
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def fun(self, reg, optype):
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rs = ""
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def a(s):
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nonlocal rs
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rs = rs + s
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a(f'def {optype}_{reg.name}(')
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printed_argument = False
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if optype == 'write':
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a('val')
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printed_argument = True
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pfun = self.print_write_register
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else:
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pfun = self.print_read_register
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if reg.num != 1:
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if printed_argument:
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a(', ')
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a('num')
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a('):\n')
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if reg.num == 1:
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a(pfun('\t', 'val', reg, None))
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else:
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for i in range(0,reg.num):
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if i == 0:
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a(f'\tif ')
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else:
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a(f'\telif ')
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a(f'num == {i}:\n')
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a(pfun('\t\t', 'val', reg, i))
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a(f'\telse:\n')
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a(f'\t\traise Exception(regnum)\n')
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a('\n')
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return rs
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def header(self):
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return "import machine\n"
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if __name__ == "__main__":
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csrh = CSRHandler(sys.argv[1], mmio_descr.registers)
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for r in mmio_descr.registers:
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csrh.update_reg(r)
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MicropythonGenerator(csrh, sys.stdout).print_file()
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print(f'picorv32_ram = const({j["memories"]["picorv32_ram"]["base"]})')
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@ -1,65 +0,0 @@
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/* Copyright 2024 (C) Peter McGoron
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* This file is a part of Upsilon, a free and open source software project.
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* For license terms, refer to the files in `doc/copying` in the Upsilon
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* source distribution.
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*
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* This BRAM can only handle aligned accesses.
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*/
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module bram #(
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/* Width of the memory bus */
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parameter BUS_WID = 32,
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/* Width of a request. */
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parameter WORD_WID = 32,
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/* Bitmask used to extract the RAM location in the buffer. */
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parameter ADDR_MASK = 32'h1FFF
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) (
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input clk,
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input wb_cyc,
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input wb_stb,
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input wb_we,
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input [4-1:0] wb_sel,
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input [BUS_WID-1:0] wb_addr,
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input [BUS_WID-1:0] wb_dat_w,
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output reg wb_ack,
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output reg [BUS_WID-1:0] wb_dat_r
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);
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initial wb_ack <= 0;
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initial wb_dat_r <= 0;
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/* When the size of the memory is a power of 2, the mask is the
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* last addressable index in the array.
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*
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* Since this buffer stores words, this is divided by 4 (32 bits).
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* When accessing a single byte, the address
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* 0b......Xab
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* is shifted to the right by two bits, throwing away "ab". This indexes
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* the 32 bit word that contains the address. This applies to halfwords
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* and words as long as the accesses are aligned.
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*/
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(* ram_style = "block" *)
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reg [WORD_WID-1:0] buffer [(ADDR_MASK >> 2):0];
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/* Current index into the buffer. */
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wire [13-1:0] ind = (wb_addr & ADDR_MASK) >> 2;
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always @ (posedge clk) if (wb_cyc && wb_stb && !wb_ack) begin
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wb_ack <= 1;
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if (wb_we) begin
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if (wb_sel[0])
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buffer[ind][7:0] <= wb_dat_w[7:0];
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if (wb_sel[1])
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buffer[ind][15:8] <= wb_dat_w[15:8];
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if (wb_sel[2])
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buffer[ind][23:16] <= wb_dat_w[23:16];
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if (wb_sel[3])
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buffer[ind][31:24] <= wb_dat_w[31:24];
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end else begin
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wb_dat_r <= buffer[ind];
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end
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end else if (!wb_stb) begin
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wb_ack <= 0;
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end
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endmodule
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@ -2892,6 +2892,8 @@ module picorv32_wb #(
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output trace_valid,
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output [35:0] trace_data,
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output debug_state,
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output mem_instr
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);
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wire mem_valid;
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@ -2989,6 +2991,7 @@ module picorv32_wb #(
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localparam WBEND = 2'b10;
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reg [1:0] state;
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assign debug_state = state;
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wire we;
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assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
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115
gateware/soc.py
115
gateware/soc.py
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@ -3,6 +3,9 @@
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# Portions of this file incorporate code licensed under the
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# BSD 2-Clause License.
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#
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# Copyright (c) 2014-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
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# Copyright (c) 2019 Gabriel L. Somlo <somlo@cmu.edu>
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# Copyright (c) 2022 Victor Suarez Rovere <suarezvictor@gmail.com>
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@ -50,7 +53,7 @@ from litex.soc.integration.soc_core import SoCCore
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from litex.soc.integration.soc import SoCRegion, SoCBusHandler, SoCIORegion
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from litex.soc.cores.clock import S7PLL, S7IDELAYCTRL
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from litex.soc.interconnect.csr import AutoCSR, Module, CSRStorage, CSRStatus
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from litex.soc.interconnect.wishbone import Interface
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from litex.soc.interconnect.wishbone import Interface, SRAM, InterconnectShared
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from litedram.phy import s7ddrphy
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from litedram.modules import MT41K128M16
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@ -153,23 +156,29 @@ class PreemptiveInterface(Module, AutoCSR):
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the combinatorial block, the If statement is constructed in a
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for loop.
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The "assign_for_case" function constructs the body of the If
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statement. It assigns all output ports to avoid latches.
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Avoiding latches:
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Left hand sign (assignment) is always an input.
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"""
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def assign_for_case(i):
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def assign_for_case(current_case):
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asn = [ ]
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for j in range(masters_len):
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if current_case == j:
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asn += [
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self.buses[i].cyc.eq(self.slave.bus.cyc if i == j else 0),
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self.buses[i].stb.eq(self.slave.bus.stb if i == j else 0),
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self.buses[i].we.eq(self.slave.bus.we if i == j else 0),
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self.buses[i].sel.eq(self.slave.bus.sel if i == j else 0),
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self.buses[i].adr.eq(self.slave.bus.adr if i == j else 0),
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self.buses[i].dat_w.eq(self.slave.bus.dat_w if i == j else 0),
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self.buses[i].ack.eq(self.slave.bus.ack if i == j else 0),
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self.buses[i].dat_r.eq(self.slave.bus.dat_r if i == j else 0),
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self.slave.bus.adr.eq(self.buses[j].adr),
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self.slave.bus.dat_w.eq(self.buses[j].dat_w),
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self.slave.bus.cyc.eq(self.buses[j].cyc),
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self.slave.bus.stb.eq(self.buses[j].stb),
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self.slave.bus.we.eq(self.buses[j].we),
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self.slave.bus.sel.eq(self.buses[j].sel),
|
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self.buses[j].dat_r.eq(self.slave.bus.dat_r),
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self.buses[j].ack.eq(self.slave.bus.ack),
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]
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else:
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asn += [
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self.buses[j].dat_r.eq(0),
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self.buses[j].ack.eq(self.buses[j].cyc & self.buses[j].stb),
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]
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return asn
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@ -190,7 +199,7 @@ class SPIMaster(Module):
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spi_cycle_half_wait = 1,
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):
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self.bus = Interface(data_width = 32, address_width=32, addressing="byte")
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self.bus = Interface(data_width = 32, address_width=32, addressing="word")
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self.region = SoCRegion(size=0x10, cached=False)
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|
||||
self.comb += [
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|
|
@ -262,48 +271,20 @@ class ControlLoopParameters(Module, AutoCSR):
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)
|
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]
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|
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class BRAM(Module):
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""" A BRAM (block ram) is a memory store that is completely separate from
|
||||
the system RAM. They are much smaller.
|
||||
"""
|
||||
def __init__(self, addr_mask, origin=None):
|
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"""
|
||||
:param addr_mask: Mask which defines the amount of bytes accessable
|
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by the BRAM.
|
||||
:param origin: Origin of the BRAM module region. This is seen by the
|
||||
subordinate master, not the usual master.
|
||||
"""
|
||||
self.bus = Interface(data_width=32, address_width=32, addressing="byte")
|
||||
|
||||
# Non-IO (i.e. MMIO) regions need to be cached
|
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self.region = SoCRegion(origin=origin, size=addr_mask+1, cached=True)
|
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|
||||
self.specials += Instance("bram",
|
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p_ADDR_MASK = addr_mask,
|
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i_clk = ClockSignal(),
|
||||
i_wb_cyc = self.bus.cyc,
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i_wb_stb = self.bus.stb,
|
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i_wb_we = self.bus.we,
|
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i_wb_sel = self.bus.sel,
|
||||
i_wb_addr = self.bus.adr,
|
||||
i_wb_dat_w = self.bus.dat_w,
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o_wb_ack = self.bus.ack,
|
||||
o_wb_dat_r = self.bus.dat_r,
|
||||
)
|
||||
|
||||
class PicoRV32(Module, AutoCSR):
|
||||
def __init__(self, bramwid=0x1000):
|
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self.submodules.params = params = ControlLoopParameters()
|
||||
self.submodules.bram = self.bram = bram = BRAM(bramwid-1, origin=0x10000)
|
||||
self.submodules.bram_iface = self.bram_iface = bram_iface = PreemptiveInterface(2, bram)
|
||||
self.submodules.ram = self.ram = SRAM(bramwid)
|
||||
ram_region = SoCRegion(size=bramwid, origin=0x10000, cached=True)
|
||||
self.submodules.ram_iface = self.ram_iface = ram_iface = PreemptiveInterface(2, self.ram)
|
||||
|
||||
# This is the PicoRV32 master
|
||||
self.masterbus = Interface(data_width=32, address_width=32, addressing="byte")
|
||||
|
||||
self.resetpin = CSRStorage(1, name="picorv32_reset", description="PicoRV32 reset")
|
||||
self.trap = CSRStatus(1, name="picorv32_trap", description="Trap bit")
|
||||
self.resetpin = CSRStorage(1, name="enable", description="PicoRV32 enable")
|
||||
self.trap = CSRStatus(1, name="trap", description="Trap bit")
|
||||
|
||||
self.ic = ic = SoCBusHandler(
|
||||
self.bus = bus = SoCBusHandler(
|
||||
standard="wishbone",
|
||||
data_width=32,
|
||||
address_width=32,
|
||||
|
|
@ -317,9 +298,14 @@ class PicoRV32(Module, AutoCSR):
|
|||
},
|
||||
)
|
||||
|
||||
ic.add_slave("picorv32_bram", bram_iface.buses[1], bram.region)
|
||||
ic.add_slave("picorv32_params", params.bus, params.region)
|
||||
ic.add_master("picorv32_master", self.masterbus)
|
||||
self.ram_stb_cyc = CSRStatus(2)
|
||||
self.ram_adr = CSRStatus(32)
|
||||
self.comb += self.ram_stb_cyc.status.eq(ram_iface.buses[1].stb << 1 | ram_iface.buses[1].cyc)
|
||||
self.comb += self.ram_adr.status.eq(ram_iface.buses[1].adr)
|
||||
|
||||
bus.add_slave("picorv32_ram", ram_iface.buses[1], ram_region)
|
||||
bus.add_slave("picorv32_params", params.bus, params.region)
|
||||
bus.add_master("picorv32_master", self.masterbus)
|
||||
|
||||
# NOTE: need to compile to these extact instructions
|
||||
self.specials += Instance("picorv32_wb",
|
||||
|
|
@ -355,14 +341,24 @@ class PicoRV32(Module, AutoCSR):
|
|||
|
||||
o_trace_valid = Signal(),
|
||||
o_trace_data = Signal(36),
|
||||
o_debug_state = Signal(2),
|
||||
)
|
||||
|
||||
# dumb hack: "self.bus.finalize()" in do_finalize()
|
||||
# should work but doesn't
|
||||
self.submodules.picobus = InterconnectShared(
|
||||
list(self.bus.masters.values()),
|
||||
slaves = [(self.bus.regions[n].decoder(self.bus), s) for n, s in self.bus.slaves.items()],
|
||||
register = self.bus.interconnect_register,
|
||||
timeout_cycles = self.bus.timeout,
|
||||
)
|
||||
|
||||
def do_finalize(self):
|
||||
self.ic.finalize()
|
||||
#self.bus.finalize()
|
||||
jsondata = {}
|
||||
|
||||
for region in self.ic.regions:
|
||||
d = self.ic.regions[region]
|
||||
for region in self.bus.regions:
|
||||
d = self.bus.regions[region]
|
||||
jsondata[region] = {
|
||||
"origin": d.origin,
|
||||
"size": d.size,
|
||||
|
|
@ -411,13 +407,10 @@ class UpsilonSoC(SoCCore):
|
|||
self.add_constant(f"{ip_name}{seg_num}", int(ip_byte))
|
||||
|
||||
def add_picorv32(self):
|
||||
self.submodules.picorv32 = pr = PicoRV32()
|
||||
self.bus.add_slave("picorv32_master_bram", pr.bram_iface.buses[0],
|
||||
SoCRegion(origin=None,size=pr.bram.region.size, cached=True))
|
||||
|
||||
def add_bram(self):
|
||||
self.submodules.bram = br = BRAM(0x1FF)
|
||||
self.bus.add_slave("bram", br.bus, br.region)
|
||||
siz = 0x1000
|
||||
self.submodules.picorv32 = pr = PicoRV32(siz)
|
||||
self.bus.add_slave("picorv32_ram", pr.ram_iface.buses[0],
|
||||
SoCRegion(origin=None,size=siz, cached=True))
|
||||
|
||||
def __init__(self,
|
||||
variant="a7-100",
|
||||
|
|
@ -445,7 +438,6 @@ class UpsilonSoC(SoCCore):
|
|||
platform.add_source("rtl/spi/spi_master_preprocessed.v")
|
||||
platform.add_source("rtl/spi/spi_master_ss.v")
|
||||
platform.add_source("rtl/spi/spi_master_ss_wb.v")
|
||||
platform.add_source("rtl/bram/bram.v")
|
||||
|
||||
# SoCCore does not have sane defaults (no integrated rom)
|
||||
SoCCore.__init__(self,
|
||||
|
|
@ -503,7 +495,6 @@ class UpsilonSoC(SoCCore):
|
|||
)
|
||||
self.bus.add_slave("spi0", self.spi0.bus, self.spi0.region)
|
||||
|
||||
self.add_bram()
|
||||
self.add_picorv32()
|
||||
|
||||
def main():
|
||||
|
|
|
|||
|
|
@ -0,0 +1,25 @@
|
|||
import machine
|
||||
from mmio import *
|
||||
|
||||
def read_file(filename):
|
||||
with open(filename, 'rb') as f:
|
||||
return f.read()
|
||||
|
||||
def run_program(prog, cl_I):
|
||||
# Reset PicoRV32
|
||||
machine.mem32[picorv32_enable] = 0
|
||||
machine.mem32[picorv32_ram_iface_master_select] = 0
|
||||
|
||||
offset = picorv32_ram
|
||||
for b in prog:
|
||||
machine.mem8[offset] = b
|
||||
offset += 1
|
||||
|
||||
for i in range(len(prog)):
|
||||
assert machine.mem8[picorv32_ram + i] == prog[i]
|
||||
|
||||
machine.mem32[picorv32_ram_iface_master_select] = 1
|
||||
assert machine.mem8[picorv32_ram] == 0
|
||||
machine.mem32[picorv32_params_cl_I] = cl_I
|
||||
machine.mem32[picorv32_enable] = 1
|
||||
return machine.mem32[picorv32_params_zset]
|
||||
|
|
@ -4,7 +4,9 @@ void _start(void)
|
|||
{
|
||||
volatile uint32_t *write = (volatile uint32_t *)(0x100000 + 0x10);
|
||||
volatile uint32_t *read = (volatile uint32_t *)( 0x100000 + 0x0);
|
||||
volatile uint32_t *next_read = (volatile uint32_t *)(0x100FF);
|
||||
*write = *read;
|
||||
*next_read = 0xdeadbeef;
|
||||
|
||||
for (;;) ;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue