Peter McGoron
06cf8807c3
1) The PicoRV32 bus was not generated correctly. Running "finalize" on the bus, which is what the SoC does, does not generate the bus logic correctly. I don't know if this is a bug or if the SoC bus generator is only meant to be used in the main SoC. Currently the bus logic is copied from the LiteX finalize code. 2) Add test micropython code to load code. 3) Removed BRAM. The Wishbone cache was messing with the direct implementation of the BRAM because the BRAM did not implement all the bus features correctly. LiteX has a Wishbone "SRAM" module, and despite it's name it can also generate BRAM if there are available BRAM. This is how the ROM and the startup RAM are implemented. The PicoRV32 ram is now using this SRAM. |
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| boot | ||
| build | ||
| buildroot | ||
| client | ||
| doc | ||
| gateware | ||
| linux | ||
| opensbi/litex/vexriscv | ||
| swic | ||
| .gitignore | ||
| README.md | ||
README.md
upsilon
Upsilon is a 100% free and open source STM/AFM controller for FPGAs running Linux. Read doc/copying/README.md for license information.
Quickstart
Read doc/docker.md to set up the Docker build environment.
Project Organization
- boot: This folder is the central place for all built files. This includes the kernel image, rootfs, gateware, etc. This directory also includes everything the TFTP server has to access.
- build: Docker build environment.
- buildroot: Buildroot configuration files.
- doc: Documentation.
- doc/copying: Licenses.
- gateware: FPGA source.
- gateware/rtl: Verilog sources.
- gateware/rtl/spi: SPI code (from another repo)
- linux: Software that runs on the controller.
- opensbi: OpenSBI configuration files and source fragments.
- swic: Code that runs on the PicoRV32 soft core.