Lab_NHMFL
/
upsilon
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

firmware/soc.py: switch to VexRiscV-SMP (with one core) to make litex happy

This commit is contained in:
Peter McGoron 2023-05-30 17:32:04 -04:00
parent 7e42b8c41c
commit 24f66c1a70
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
firmware/soc.py
View File

@ -259,7 +259,9 @@ class UpsilonSoC(SoCCore):
bus_data_width = 32, bus_data_width = 32,
bus_address_width = 32, bus_address_width = 32,
bus_timeout = int(1e6), bus_timeout = int(1e6),
cpu_type = "vexriscv", cpu_type = "vexriscv_smp",
cpu_count = 1,
cpu_variant="linux",
integrated_rom_size=0x20000, integrated_rom_size=0x20000,
integrated_sram_size = 0x2000, integrated_sram_size = 0x2000,
csr_data_width=32, csr_data_width=32,