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firmware/soc.py: switch to VexRiscV-SMP (with one core) to make litex happy

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Peter McGoron 2023-05-30 17:32:04 -04:00
parent 7e42b8c41c
commit 24f66c1a70
1 changed files with 3 additions and 1 deletions
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firmware/soc.py
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@ -259,7 +259,9 @@ class UpsilonSoC(SoCCore):
bus_data_width = 32,
bus_address_width = 32,
bus_timeout = int(1e6),
cpu_type = "vexriscv",
cpu_type = "vexriscv_smp",
cpu_count = 1,
cpu_variant="linux",
integrated_rom_size=0x20000,
integrated_sram_size = 0x2000,
csr_data_width=32,