make lawyers happy
This commit is contained in:
parent
cd3f6d8cf9
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# Copyright 2023 Peter McGoron
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# Copyright 2023 (C) Peter McGoron
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
|
||||
#
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# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
# This file is a part of Upsilon, a free and open source software project.
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||||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
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# source distribution.
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FROM debian:bookworm
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@ -1,18 +1,8 @@
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# Copyright 2023 Peter McGoron
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# Copyright 2023 (C) Peter McGoron
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
# This file is a part of Upsilon, a free and open source software project.
|
||||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
# source distribution.
|
||||
|
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FROM debian:bookworm
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|
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@ -1,18 +1,8 @@
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# Copyright 2023 Peter McGoron
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# Copyright 2023 (C) Peter McGoron
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
# This file is a part of Upsilon, a free and open source software project.
|
||||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
# source distribution.
|
||||
|
||||
FROM debian:bookworm
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|
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|
|
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@ -1,18 +1,8 @@
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# Copyright 2023 Peter McGoron
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# Copyright 2023 (C) Peter McGoron
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
# This file is a part of Upsilon, a free and open source software project.
|
||||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
# source distribution.
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||||
|
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FROM debian:bookworm
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@ -1,6 +1,8 @@
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# Copyright 2023 Peter McGoron
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# Copyright 2023 (C) Peter McGoron
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
# This file is a part of Upsilon, a free and open source software project.
|
||||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
# source distribution.
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||||
|
||||
.PHONY: images f4pga buildroot litex clone help attach hardware-image \
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buildroot-image litex-f4pga-image \
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@ -112,7 +114,7 @@ buildroot-clean:
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###### TFTP
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tftp:
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cd upsilon/boot && py3tftp --host 192.168.1.100 -p 6969 -v
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cd ../boot && py3tftp --host 192.168.1.100 -p 6969 -v
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###### External projects
|
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@ -142,9 +144,9 @@ litex:
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git checkout -B upsilon_stable c6ccb626e88168045edacced3743f6bd98746742
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|
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upsilon-hardware.tar.gz:
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tar -czvf upsilon-hardware.tar.gz ../gateware/
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tar -czvf upsilon-hardware.tar.gz ../gateware/ --transform 's|gateware|upsilon/gateware|'
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upsilon-buildroot.tar.gz:
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tar -czvf upsilon-buildroot.tar.gz ../buildroot/
|
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tar -czvf upsilon-buildroot.tar.gz ../buildroot/ --transform 's|buildroot|upsilon/buildroot|'
|
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# This script only works for GNU tar. It renames the extraction directory.
|
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upsilon-opensbi.tar.gz:
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tar -czvf upsilon-opensbi.tar.gz ../opensbi/ --transform 's|opensbi|opensbi/platform|'
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|
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@ -1,3 +1,9 @@
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# Copyright 2023 (C) Peter McGoron
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#
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# This file is a part of Upsilon, a free and open source software project.
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# For license terms, refer to the files in `doc/copying` in the Upsilon
|
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# source distribution.
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CONFIG_SECTION_MISMATCH_WARN_ONLY=y
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# Architecture
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|
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@ -1,3 +1,8 @@
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# Copyright 2023 (C) Peter McGoron
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# This file is a part of Upsilon, a free and open source software project.
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||||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
# source distribution.
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||||
#
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||||
#Target options
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BR2_riscv=y
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BR2_RISCV_32=y
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@ -1,5 +1,12 @@
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Upsilon is a copyleft hardware project, which brings its own difficulties.
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Upsilon is dual-licensed in many locations.
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||||
Copyright (C) Peter McGoron
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||||
|
||||
This file is a part of Upsilon, a free and open source software project.
|
||||
For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
source distribution.
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||||
|
||||
__________________________________________________________________________
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|
||||
Upsilon is governed by multiple open-source licenses.
|
||||
|
||||
The files under `gateware/` are disjunctive dual-licensed under the CERN-OHL-S
|
||||
v2.0 (or any later version), or the GNU GPL v3.0 (or any later version).
|
||||
|
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@ -23,3 +30,16 @@ Any other file is licensed under the GNU GPL v3.0 (or any later version).
|
|||
|
||||
Some files contain additional licenses. You must comply with the terms of
|
||||
both the license in a file and the licenses specified here.
|
||||
|
||||
## Guidelines
|
||||
|
||||
Each file should have the following header in a comment:
|
||||
|
||||
Copyright year (C) John Doe
|
||||
Copyright year (C) Jane Doe
|
||||
...
|
||||
This file is a part of Upsilon, a free and open source software project.
|
||||
For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
source distribution.
|
||||
|
||||
Add your name to files that you have added a notable amount to.
|
||||
|
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@ -1,3 +1,9 @@
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|||
# Copyright 2023 (C) Peter McGoron
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||||
#
|
||||
# This file is a part of Upsilon, a free and open source software project.
|
||||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
# source distribution.
|
||||
#
|
||||
.PHONY: cpu clean rtl_codegen
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DEVICETREE_GEN_DIR=.
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@ -1,3 +1,8 @@
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# Copyright 2023 (C) Peter McGoron
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||||
# This file is a part of Upsilon, a free and open source software project.
|
||||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
# source distribution.
|
||||
|
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all: make_base make_spi make_control_loop
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|
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test:
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|
|
|
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|
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@ -2,6 +2,13 @@ m4_changequote(`⟨', `⟩')
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m4_changecom(⟨/*⟩, ⟨*/⟩)
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m4_define(generate_macro, ⟨m4_define(M4_$1, $2)⟩)
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||||
m4_include(../control_loop/control_loop_cmds.m4)
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/*
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# Copyright 2023 (C) Peter McGoron
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||||
#
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||||
# This file is a part of Upsilon, a free and open source software project.
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||||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
# source distribution.
|
||||
*/
|
||||
|
||||
/* Since yosys only allows for standard Verilog (no system verilog),
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* arrays (which would make everything much cleaner) cannot be used.
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@ -1,3 +1,8 @@
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# Copyright 2023 (C) Peter McGoron
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# This file is a part of Upsilon, a free and open source software project.
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||||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
# source distribution.
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||||
|
||||
# Generate verilog from m4 file
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#m4 -P --synclines $< | awk -v filename=$< '/^#line/ {printf("`line %d %s 0\n", $$2, filename); next} {print}' > $@
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||||
# NOTE: f4pga yosys does not support `line directives. Use above for debug.
|
||||
|
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|
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@ -1,3 +1,8 @@
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# Copyright 2023 (C) Peter McGoron
|
||||
# This file is a part of Upsilon, a free and open source software project.
|
||||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
# source distribution.
|
||||
|
||||
# Makefile for tests and hardware verification.
|
||||
|
||||
.PHONY: test clean codegen all
|
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|
|
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|
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@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
module adc_sim #(
|
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parameter POLARITY = 1,
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parameter PHASE = 0,
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|
|
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|
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@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
/* Booth Multiplication v1.1
|
||||
* Written by Peter McGoron, 2022.
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||||
*
|
||||
|
|
|
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|
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@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
#include <memory>
|
||||
#include <limits>
|
||||
#include <cstdint>
|
||||
|
|
|
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|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
m4_changequote(`⟨', `⟩')
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m4_changecom(⟨/*⟩, ⟨*/⟩)
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m4_define(generate_macro, ⟨m4_define(M4_$1, $2)⟩)
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|
|
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|
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@ -1,3 +1,8 @@
|
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/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
m4_changequote(`⟨', `⟩')m4_dnl
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m4_changecom(⟨/*⟩, ⟨*/⟩)m4_dnl
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m4_define(generate_macro, ⟨m4_dnl
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|
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|
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@ -1,3 +1,8 @@
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/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
generate_macro(CONTROL_LOOP_NOOP, 0)
|
||||
generate_macro(CONTROL_LOOP_STATUS, 1)
|
||||
generate_macro(CONTROL_LOOP_SETPT, 2)
|
||||
|
|
|
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|
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@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
m4_changequote(`⟨', `⟩')m4_dnl
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||||
m4_changecom(⟨/*⟩, ⟨*/⟩)m4_dnl
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m4_define(generate_macro, ⟨m4_dnl
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||||
|
|
|
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|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
m4_changequote(`⟨', `⟩')
|
||||
m4_changecom(⟨/*⟩, ⟨*/⟩)
|
||||
/*************** Precision **************
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
#include "control_loop_math_implementation.h"
|
||||
|
||||
#define BITMASK(n) (((V)1 << (n)) - 1)
|
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|
|
|
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|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
#pragma once
|
||||
#include <cstdint>
|
||||
#include <string>
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
/* TODO: add ADC_TO_DAC multiplication and verify */
|
||||
#include <cstdio>
|
||||
#include <cstdint>
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
#include <memory>
|
||||
#include <limits>
|
||||
#include <cstdint>
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
/* Copyright 2022 (C) Peter McGoron
|
||||
* Copyright 2022 (C) Nicolas Azzi
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
#include <memory>
|
||||
#include <limits>
|
||||
#include <cstdint>
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
`include "control_loop_cmds.vh"
|
||||
|
||||
module control_loop_sim_top #(
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
module dac_sim #(
|
||||
parameter POLARITY = 0,
|
||||
parameter PHASE = 1,
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
/* Saturate integers. v0.1
|
||||
* Written by Peter McGoron, 2022.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
#include <memory>
|
||||
#include <limits>
|
||||
#include <cstdint>
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
//testbench for intsat module
|
||||
//Timothy Burman, 2022
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
module sign_extend #(
|
||||
parameter WID1 = 18,
|
||||
parameter WID2 = 24
|
||||
|
|
|
|||
|
|
@ -1 +0,0 @@
|
|||
yosys -p "plugin -i systemverilog" -p "read_systemverilog control_loop.v control_loop_math.v ../spi/spi_master_ss_no_write.v ../spi/spi_master_ss.v boothmul.v intsat.v ../spi/spi_master.v ../spi/spi_master_no_write.v" -p "synth_xilinx"
|
||||
|
|
@ -1,3 +1,8 @@
|
|||
# Copyright 2023 (C) Peter McGoron
|
||||
# This file is a part of Upsilon, a free and open source software project.
|
||||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
# source distribution.
|
||||
#
|
||||
# Makefile for tests and hardware verification.
|
||||
|
||||
.PHONY: test clean
|
||||
|
|
|
|||
|
|
@ -1,17 +0,0 @@
|
|||
# Clock pin
|
||||
set_property PACKAGE_PIN E3 [get_ports {clk}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {clk}]
|
||||
|
||||
set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
|
||||
set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
|
||||
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
|
||||
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
|
||||
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
|
||||
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
|
||||
set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
|
||||
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
|
||||
set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
|
||||
set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
|
||||
|
||||
# Clock constraints
|
||||
create_clock -period 10.0 [get_ports {clk}]
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
{
|
||||
"default_part": "XC7A35TCSG324-1",
|
||||
"values": {
|
||||
"top": "top"
|
||||
},
|
||||
"dependencies": {
|
||||
"sources": [
|
||||
"synth_test_top.v",
|
||||
"ram_fifo_dual_port.v",
|
||||
"ram_fifo.v"
|
||||
],
|
||||
"synth_log": "synth.log",
|
||||
"pack_log": "pack.log"
|
||||
},
|
||||
"XC7A35TCSG324-1": {
|
||||
"default_target": "bitstream",
|
||||
"dependencies": {
|
||||
"build_dir": "build/arty_35",
|
||||
"xdc": [
|
||||
"arty.xdc"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
/* Implements a synchronous(!) FIFO using inferred Block RAM. This
|
||||
* must wrap "ram_fifo_dual_port" due to difficulties YOSYS has with
|
||||
* inferring Block RAM: refer to that module for details.
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
/* YOSYS has a difficult time infering single port BRAM. It can infer
|
||||
* double-port block ram, however. This module is written as a double
|
||||
* port block ram, even though both clocks will end up being the same.
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
#include <memory>
|
||||
#include <cassert>
|
||||
#include <limits>
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
/* Ram shim. This is an interface designed for a LiteX RAM DMA module.
|
||||
* It can also be connected to a simulator.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
`define RAM_SHIM_NO_OP 0
|
||||
`define RAM_SHIM_WRITE_LOC 1
|
||||
`define RAM_SHIM_WRITE_LEN 2
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
#include <memory>
|
||||
#include <cassert>
|
||||
#include <limits>
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
/* Raster scanner. This module sweeps two DACs (the X and Y piezos)
|
||||
* across a box, where the X and Y axes may be at an angle. After
|
||||
* a single step, the ADCs connected to the raster scanner are
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
`define RASTER_NOOP 0
|
||||
`define RASTER_MAX_SAMPLES 1
|
||||
`define RASTER_MAX_LINES 2
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
#include <limits>
|
||||
#include <cstdint>
|
||||
#include <cstring>
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
`timescale 10ns/10ns
|
||||
`include "raster_cmds.vh"
|
||||
`include "ram_shim_cmds.vh"
|
||||
|
|
|
|||
|
|
@ -1,4 +0,0 @@
|
|||
read_verilog raster.v
|
||||
synth_xilinx -flatten -nosrl -noclkbuf -nodsp -iopad -nowidelut
|
||||
# synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp -iopad -nowidelut
|
||||
write_verilog synth_test_yosys.v
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
module top (
|
||||
input clk,
|
||||
input [1:0] btn,
|
||||
input ck_io0,
|
||||
input ck_io1,
|
||||
input ck_io2,
|
||||
input ck_io3,
|
||||
output ck_io4,
|
||||
output ck_io5,
|
||||
output ck_io6,
|
||||
output ck_io7,
|
||||
);
|
||||
|
||||
wire bufg;
|
||||
BUFG bufgctrl (
|
||||
.I(clk),
|
||||
.O(bufg)
|
||||
);
|
||||
|
||||
ram_fifo #(.DAT_WID(4), .FIFO_DEPTH(65535/2), .FIFO_DEPTH_WID(16) ) rf (
|
||||
.clk(bufg),
|
||||
.rst(0),
|
||||
.read_enable(btn[0]),
|
||||
.write_enable(btn[1]),
|
||||
.write_dat({ck_io0,ck_io1,ck_io2,ck_io3}),
|
||||
.read_dat({ck_io4,ck_io5,ck_io6,ck_io7})
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -1,3 +1,7 @@
|
|||
# Copyright 2023 (C) Peter McGoron
|
||||
# This file is a part of Upsilon, a free and open source software project.
|
||||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
# source distribution.
|
||||
# Makefile for tests and hardware verification.
|
||||
|
||||
.PHONY: test clean codegen
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
/* Dynamically adjustable DAC ramping.
|
||||
* Given an increment voltage and a speed setting, increase the voltage
|
||||
* to that voltage in increments over a period of time.
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
/* (c) Peter McGoron 2022 v0.3
|
||||
* This Source Code Form is subject to the terms of the Mozilla Public
|
||||
* License, v.2.0. If a copy of the MPL was not distributed with this
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
`define SPI_MASTER_NO_READ
|
||||
/* verilator lint_off DECLFILENAME */
|
||||
`include "spi_master.v"
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
`define SPI_MASTER_NO_WRITE
|
||||
/* verilator lint_off DECLFILENAME */
|
||||
`include "spi_master.v"
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
`define SPI_MASTER_SS_NAME spi_master_ss
|
||||
`define SPI_MASTER_NAME spi_master
|
||||
/* verilator lint_off DECLFILENAME */
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
`define SPI_MASTER_SS_NAME spi_master_ss_no_read
|
||||
`define SPI_MASTER_NAME spi_master_no_read
|
||||
`define SPI_MASTER_NO_READ
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
`define SPI_MASTER_SS_NAME spi_master_ss_no_write
|
||||
`define SPI_MASTER_NAME spi_master_no_write
|
||||
`define SPI_MASTER_NO_WRITE
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
/* (c) Peter McGoron 2022 v0.3
|
||||
* This Source Code Form is subject to the terms of the Mozilla Public
|
||||
* License, v.2.0. If a copy of the MPL was not distributed with this
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
/* (c) Peter McGoron 2022 v0.3
|
||||
* This Source Code Form is subject to the terms of the Mozilla Public
|
||||
* License, v.2.0. If a copy of the MPL was not distributed with this
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
`define SPI_SLAVE_NO_READ
|
||||
/* verilator lint_off DECLFILENAME */
|
||||
`include "spi_slave.v"
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
`define SPI_SLAVE_NO_WRITE
|
||||
/* verilator lint_off DECLFILENAME */
|
||||
`include "spi_slave.v"
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
/* This module is a co-operative crossbar for the wires only. Each end
|
||||
* implements its own SPI master.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
#include "../util.hpp"
|
||||
#include "Vspi_switch.h"
|
||||
Vspi_switch *tb;
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
#pragma once
|
||||
#include <verilated.h>
|
||||
#include "util.hpp"
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
#pragma once
|
||||
#include <cstdarg>
|
||||
#include <cstdlib>
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
# Copyright 2023 (C) Peter McGoron
|
||||
# This file is a part of Upsilon, a free and open source software project.
|
||||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
# source distribution.
|
||||
|
||||
# Makefile for tests and hardware verification.
|
||||
|
||||
include ../common.makefile
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
#include "bram_dma.hpp"
|
||||
#include "../util.hpp"
|
||||
#include <cstdlib>
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
#pragma once
|
||||
#include <cstddef>
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
module bram_interface #(
|
||||
parameter WORD_WID = 24,
|
||||
parameter WORD_AMNT_WID = 11,
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
#include <limits>
|
||||
#include <cstdlib>
|
||||
#include <random>
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
module bram_interface_sim #(
|
||||
parameter WORD_WID = 20,
|
||||
parameter WORD_AMNT_WID = 11,
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
/* This module is used to simulate direct memory access, where only
|
||||
* a small amount of memory is valid to read.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
/* Write a waveform to a DAC. */
|
||||
/* TODO: Add "how many values to go" counter. */
|
||||
module waveform #(
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
/* TODO: impleement reset for dma and test both separetely */
|
||||
#include <vector>
|
||||
#include "Vwaveform_sim.h"
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
/* Copyright 2023 (C) Peter McGoron
|
||||
* This file is a part of Upsilon, a free and open source software project.
|
||||
* For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
* source distribution.
|
||||
*/
|
||||
module waveform_sim #(
|
||||
parameter DAC_WID = 24,
|
||||
parameter DAC_WID_SIZ = 5,
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
"""
|
||||
##########################################################################
|
||||
# Portions of this file incorporate code licensed under the
|
||||
# BSD 2-Clause License.
|
||||
|
|
@ -32,6 +33,12 @@
|
|||
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
##########################################################################
|
||||
# Copyright 2023 (C) Peter McGoron
|
||||
#
|
||||
# This file is a part of Upsilon, a free and open source software project.
|
||||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
# source distribution.
|
||||
"""
|
||||
|
||||
# There is nothing fundamental about the Arty A7(35|100)T to this
|
||||
# design, but another eval board will require some porting.
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
# SPDX-License-Identifier: BSD-2-Clause
|
||||
# Copyright 2023 (C) Peter McGoron
|
||||
|
||||
config PLATFORM_LITEX_VEXRISCV
|
||||
bool
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
#
|
||||
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
# Copyright (c) 2020 Dolu1990 <charles.papon.90@gmail.com>
|
||||
# Copyright (c) 2023 Peter McGoron
|
||||
#
|
||||
|
||||
# Command for platform specific "make run"
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
#
|
||||
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
# Copyright (c) 2020 Dolu1990 <charles.papon.90@gmail.com>
|
||||
# Copyright (c) 2023 Peter McGoron
|
||||
#
|
||||
|
||||
# Command for platform specific "make run"
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Dolu1990 <charles.papon.90@gmail.com>
|
||||
* Copyright (C) 2023 Peter McGoron
|
||||
*
|
||||
*/
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue