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GUIDELINES.md

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Peter McGoron 2023-04-21 14:26:37 -04:00
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@ -29,6 +29,7 @@ See also [Dan Gisselquist][1]'s rules for FPGA development.
takes care of connecting modules together and assigning each register takes care of connecting modules together and assigning each register
a memory location. a memory location.
* Keep all Verilog as generic as possible. * Keep all Verilog as generic as possible.
* Always initialize registers.
# Software # Software