change heading

2022-10-22 01:55:56 -04:00 · 2022-10-22 01:55:56 -04:00 · 7971f8ea98
parent 644929ef8a
commit 7971f8ea98
1 changed files with 2 additions and 1 deletions
--- a/firmware/rtl/control_loop/intro.md
+++ b/firmware/rtl/control_loop/intro.md
@ -28,7 +28,8 @@ cycle, which in turn requires knowing the ADC and DAC timings.  This
 is done outside the Verilog code.  and can be calculated from
 simulating one iteration of the control loop.

-************** Fixed Point Integers************
+# Fixed Point Integers
+
 A regular number is stored in decimal: 123056.
 This is equal to