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Peter McGoron 2022-10-22 01:55:56 -04:00
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firmware/rtl/control_loop/intro.md
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@ -28,7 +28,8 @@ cycle, which in turn requires knowing the ADC and DAC timings. This
is done outside the Verilog code. and can be calculated from is done outside the Verilog code. and can be calculated from
simulating one iteration of the control loop. simulating one iteration of the control loop.
************** Fixed Point Integers************ # Fixed Point Integers
A regular number is stored in decimal: 123056. A regular number is stored in decimal: 123056.
This is equal to This is equal to