merge

.gitignore

@@ -20,3 +20,14 @@ firmware/rtl/control_loop/control_loop.v
 firmware/rtl/control_loop/control_loop_cmds.vh
 firmware/rtl/control_loop/control_loop_math.v
 *_preprocessed.v
+firmware/csr.repl
+firmware/csr.resc
+firmware/rtl/control_loop/slpp_all/
+firmware/rtl/raster/.f4cache
+firmware/rtl/raster/build/
+firmware/rtl/raster/pack.log
+firmware/rtl/raster/place.log
+firmware/rtl/raster/route.log
+firmware/rtl/raster/synth.log
+firmware/rtl/raster/synth_test_yosys.v
+firmware/rtl/raster/yosys_output

creole

@@ -1 +1 @@
-Subproject commit 945bcd68a54ebf6794fa791545426e5f29644029
+Subproject commit 6d30be57f7c1853eb1fe26e91e0d0aae8811383b

firmware/rtl/control_loop/yosys_test.sh

@@ -0,0 +1 @@
+yosys -p "plugin -i systemverilog" -p "read_systemverilog control_loop.v control_loop_math.v ../spi/spi_master_ss_no_write.v ../spi/spi_master_ss.v boothmul.v intsat.v ../spi/spi_master.v ../spi/spi_master_no_write.v" -p "synth_xilinx"

firmware/rtl/raster/arty.xdc

@@ -0,0 +1,17 @@
+# Clock pin
+set_property PACKAGE_PIN E3 [get_ports {clk}]
+set_property IOSTANDARD LVCMOS33 [get_ports {clk}]
+
+set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
+set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
+set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { ck_io0  }]; #IO_L16P_T2_CSI_B_14          Sch=ck_io[0]
+set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { ck_io1  }]; #IO_L18P_T2_A12_D28_14        Sch=ck_io[1]
+set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { ck_io2  }]; #IO_L8N_T1_D12_14             Sch=ck_io[2]
+set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { ck_io3  }]; #IO_L19P_T3_A10_D26_14        Sch=ck_io[3]
+set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { ck_io4  }]; #IO_L5P_T0_D06_14             Sch=ck_io[4]
+set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { ck_io5  }]; #IO_L14P_T2_SRCC_14           Sch=ck_io[5]
+set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { ck_io6  }]; #IO_L14N_T2_SRCC_14           Sch=ck_io[6]
+set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { ck_io7  }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
+
+# Clock constraints
+create_clock -period 10.0 [get_ports {clk}]

firmware/rtl/raster/flow.json

@@ -0,0 +1,24 @@
+{
+    "default_part": "XC7A35TCSG324-1",
+    "values": {
+        "top": "top"
+    },
+    "dependencies": {
+        "sources": [
+            "synth_test_top.v",
+	    "ram_fifo_dual_port.v",
+	    "ram_fifo.v"
+        ],
+        "synth_log": "synth.log",
+        "pack_log": "pack.log"
+    },
+    "XC7A35TCSG324-1": {
+        "default_target": "bitstream",
+        "dependencies": {
+            "build_dir": "build/arty_35",
+            "xdc": [
+                "arty.xdc"
+            ]
+        }
+    }
+}

firmware/rtl/raster/script

@@ -0,0 +1,4 @@
+read_verilog raster.v
+synth_xilinx -flatten -nosrl -noclkbuf -nodsp -iopad -nowidelut
+# synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp -iopad -nowidelut
+write_verilog synth_test_yosys.v

firmware/rtl/raster/synth_test_top.v

@@ -0,0 +1,28 @@
+module top (
+    input clk,
+    input [1:0] btn,
+    input ck_io0,
+    input ck_io1,
+    input ck_io2,
+    input ck_io3,
+    output ck_io4,
+    output ck_io5,
+    output ck_io6,
+    output ck_io7,
+);
+
+  wire bufg;
+  BUFG bufgctrl (
+      .I(clk),
+      .O(bufg)
+  );
+
+  ram_fifo #(.DAT_WID(4), .FIFO_DEPTH(65535/2), .FIFO_DEPTH_WID(16) ) rf (
+	  .clk(bufg),
+	  .rst(0),
+	  .read_enable(btn[0]),
+	  .write_enable(btn[1]),
+	  .write_dat({ck_io0,ck_io1,ck_io2,ck_io3}),
+	  .read_dat({ck_io4,ck_io5,ck_io6,ck_io7})
+  );
+endmodule