add makefile; condense LiteX CSRs

Makefile

@@ -0,0 +1,7 @@
+.PHONY: cpu clean
+cpu: soc.py
+	python3 soc.py
+clean:
+	rm -rf build csr.json overlay.config overlay.dts
+overlay.dts overlay.config: csr.json
+	# NOTE: Broken in LiteX 2022.4.

clean.sh

@@ -1,3 +0,0 @@
-#!/bin/sh
-
-rm -rf build csr.json

soc.py

@@ -141,17 +141,17 @@ io = [
 
 class DACThroughGPIO(Module, AutoCSR):
     def __init__(self, pins):
-        self._ss = CSRStorage(1, description="Slave Select (Control)")
-        self._mosi = CSRStorage(1, description="Master Out, Slave In (Control)")
         self._miso = CSRStatus(1, description="Master In, Slave Out (Status)")
-        self._sck = CSRStorage(1, description="Serial Clock (Control)")
+        # Read as [MSB ... LSB]
+        self._ctrl = CSRStorage(3, description="SS, SCK, MOSI (Control)")
         self._pins = pins
 
-        self.comb += self._pins.ss.eq(self._ss.storage)
-        self.comb += self._pins.mosi.eq(self._mosi.storage)
-        self.comb += self._pins.sck.eq(self._sck.storage)
         self.comb += self._miso.status.eq(self._pins.miso)
 
+        self.comb += self._pins.ss.eq(~self._ctrl.storage[2])
+        self.comb += self._pins.mosi.eq(self._ctrl.storage[1])
+        self.comb += self._pins.sck.eq(self._ctrl.storage[0])
+
 class ADCThroughGPIO(Module, AutoCSR):
     def __init__(self, pins):
         self._pins = pins