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Minor SPI fixes and Interconnect fix 

The previous code did not properly assign all values on all cases,
and did not properly assign values (master interfaces, which are
poorly named because they are the interfaces to the master, connect
to the slave lines directly in the interconnect)
This commit is contained in:
Peter McGoron 2024-02-03 00:33:52 +00:00
parent 68ce1f4f64
commit 9f76e03028
3 changed files with 16 additions and 19 deletions
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4
gateware/Makefile
View File

@ -28,5 +28,5 @@ arty.dts: csr.json
arty.dtb: arty.dts
dtc -O dtb -o arty.dtb arty.dts
mmio.py: csr2mp.py csr.json
python3 csr2mp.py csr.json > mmio.py
#mmio.py: csr2mp.py csr.json
# python3 csr2mp.py csr.json > mmio.py

4
gateware/rtl/spi/spi_master_ss_wb.v
View File

@ -27,7 +27,7 @@ module spi_master_ss_wb
input miso,
output mosi,
output sck_wire,
output ss_L
output ss_L,
input wb_cyc,
input wb_stb,
@ -97,7 +97,7 @@ always @ (posedge clk) if (wb_cyc && wb_stb && !wb_ack) begin
4'h4: arm <= wb_dat_w[0];
4'hC: to_slave <= wb_dat_w;
default: ;
end
endcase
wb_ack <= 1;
end else begin
wb_ack <= 0;

27
gateware/soc.py
View File

@ -158,25 +158,21 @@ class PreemptiveInterface(Module, AutoCSR):
"""
def assign_for_case(i):
asn = [
self.slave.bus.cyc.eq(self.buses[i].cyc),
self.slave.bus.stb.eq(self.buses[i].stb),
self.slave.bus.we.eq(self.buses[i].we),
self.slave.bus.sel.eq(self.buses[i].sel),
self.slave.bus.adr.eq(self.buses[i].adr),
self.slave.bus.dat_w.eq(self.buses[i].dat_w),
self.slave.bus.ack.eq(self.buses[i].ack),
self.slave.bus.dat_r.eq(self.buses[i].dat_r),
]
asn = [ ]
for j in range(masters_len):
if j == i:
continue
asn += [
self.buses[i].ack.eq(0),
self.buses[i].ack.eq(0),
self.buses[i].cyc.eq(self.slave.bus.cyc if i == j else 0),
self.buses[i].stb.eq(self.slave.bus.stb if i == j else 0),
self.buses[i].we.eq(self.slave.bus.we if i == j else 0),
self.buses[i].sel.eq(self.slave.bus.sel if i == j else 0),
self.buses[i].adr.eq(self.slave.bus.adr if i == j else 0),
self.buses[i].dat_w.eq(self.slave.bus.dat_w if i == j else 0),
self.buses[i].ack.eq(self.slave.bus.ack if i == j else 0),
self.buses[i].dat_r.eq(self.slave.bus.dat_r if i == j else 0),
self.buses[i].cti.eq(0),
self.buses[i].bte.eq(0),
]
return asn
cases = {"default": assign_for_case(0)}
@ -401,6 +397,7 @@ class UpsilonSoC(SoCCore):
def add_picorv32(self):
self.submodules.picorv32 = pr = PicoRV32()
self.bus.add_slave("picorv32_master_bram", pr.bram_iface.buses[0], pr.bram.region)
pr.finalize()
def __init__(self,
variant="a7-100",