Minor SPI fixes and Interconnect fix
The previous code did not properly assign all values on all cases, and did not properly assign values (master interfaces, which are poorly named because they are the interfaces to the master, connect to the slave lines directly in the interconnect)
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@ -28,5 +28,5 @@ arty.dts: csr.json
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arty.dtb: arty.dts
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dtc -O dtb -o arty.dtb arty.dts
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mmio.py: csr2mp.py csr.json
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python3 csr2mp.py csr.json > mmio.py
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#mmio.py: csr2mp.py csr.json
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# python3 csr2mp.py csr.json > mmio.py
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@ -27,7 +27,7 @@ module spi_master_ss_wb
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input miso,
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output mosi,
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output sck_wire,
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output ss_L
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output ss_L,
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input wb_cyc,
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input wb_stb,
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@ -97,7 +97,7 @@ always @ (posedge clk) if (wb_cyc && wb_stb && !wb_ack) begin
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4'h4: arm <= wb_dat_w[0];
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4'hC: to_slave <= wb_dat_w;
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default: ;
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end
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endcase
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wb_ack <= 1;
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end else begin
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wb_ack <= 0;
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@ -158,25 +158,21 @@ class PreemptiveInterface(Module, AutoCSR):
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"""
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def assign_for_case(i):
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asn = [
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self.slave.bus.cyc.eq(self.buses[i].cyc),
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self.slave.bus.stb.eq(self.buses[i].stb),
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self.slave.bus.we.eq(self.buses[i].we),
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self.slave.bus.sel.eq(self.buses[i].sel),
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self.slave.bus.adr.eq(self.buses[i].adr),
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self.slave.bus.dat_w.eq(self.buses[i].dat_w),
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self.slave.bus.ack.eq(self.buses[i].ack),
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self.slave.bus.dat_r.eq(self.buses[i].dat_r),
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]
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asn = [ ]
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for j in range(masters_len):
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if j == i:
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continue
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asn += [
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self.buses[i].ack.eq(0),
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self.buses[i].ack.eq(0),
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self.buses[i].cyc.eq(self.slave.bus.cyc if i == j else 0),
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self.buses[i].stb.eq(self.slave.bus.stb if i == j else 0),
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self.buses[i].we.eq(self.slave.bus.we if i == j else 0),
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self.buses[i].sel.eq(self.slave.bus.sel if i == j else 0),
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self.buses[i].adr.eq(self.slave.bus.adr if i == j else 0),
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self.buses[i].dat_w.eq(self.slave.bus.dat_w if i == j else 0),
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self.buses[i].ack.eq(self.slave.bus.ack if i == j else 0),
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self.buses[i].dat_r.eq(self.slave.bus.dat_r if i == j else 0),
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self.buses[i].cti.eq(0),
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self.buses[i].bte.eq(0),
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]
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return asn
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cases = {"default": assign_for_case(0)}
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@ -401,6 +397,7 @@ class UpsilonSoC(SoCCore):
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def add_picorv32(self):
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self.submodules.picorv32 = pr = PicoRV32()
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self.bus.add_slave("picorv32_master_bram", pr.bram_iface.buses[0], pr.bram.region)
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pr.finalize()
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def __init__(self,
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variant="a7-100",
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