separate math into other file
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/*************** Precision **************
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* The control loop is designed around these values, but generally
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* does not hardcode them.
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*
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* Since α and P are precalculated outside of the loop, their
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* conversion to numbers the loop understands is done outside of
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* the loop and in the kernel.
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*
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* The 18-bit ADC is twos-compliment, -10.24V to 10.24V,
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* with 78μV per increment.
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* The 20-bit DAC is twos-compliment, -10V to 10V.
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*
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* The `P` constant has a minimum value of 1e-7 with a precision
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* of 1e-9, and a maxmimum value of 1.
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*
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* The `I` constant has a minimum value of 1e-4 with a precision
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* of 1e-6 and a maximum value of 100.
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*
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* Δt is cycles/100MHz. This makes Δt at least 10 ns, with a
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* maximum of 1 ms.
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*
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* [1 : sign][7: whole][40: fractional]
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* This is 127 to -128, with a resolution of 9.095e-13.
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*/
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/* If this design needs to be faster, you can:
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1) Pipeline the design
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2) Use DSPs
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With symbiflow + yosys there is no way to explicitly instantiate
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a DSP40 module. YOSYS may infer it but that might be unreliable.
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*/
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module control_loop_math #(
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parameter CONSTS_WHOLE = 8,
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parameter CONSTS_FRAC = 40,
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parameter CONSTS_WID = CONSTS_WHOLE + CONSTS_FRAC,
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/* This number is the conversion from ADC voltage units to
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* a fixed-point number.
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* A micro-optimization could roll the ADC reading and the multiplier
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* together.
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* The LSB of this number is 2**(-CONSTS_FRAC).
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*/
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parameter INT_TO_REAL_WID = 27,
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parameter [INT_TO_REAL_WID-1:0] INT_TO_REAL = 'b101000111001001111101110010,
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/* This number is 1/(clock cycle).
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The number is interpreted so the least significant bit
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coincides with the LSB of a constant. */
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parameter SEC_PER_CYCLE_WID = 14,
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parameter [SEC_PER_CYCLE_WID-1:0] SEC_PER_CYCLE = 'b10101011110011,
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parameter DELAY_WID = 16,
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parameter DAC_DATA_WID = 20,
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parameter ADC_WID = 18,
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parameter CYCLE_COUNT_WID = 18
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) (
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input clk,
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input arm,
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output finished,
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input [ADC_WID-1:0] setpt,
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input [ADC_WID-1:0] measured,
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input [CONSTS_WID-1:0] cl_P,
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input [CONSTS_WID-1:0] cl_I,
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input [CONSTS_WID-1:0] e_prev,
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input [CYCLE_COUNT_WID-1:0] cycles,
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input [DELAY_WID-1:0] dely,
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output reg [CONSTS_WID-1:0] e_cur,
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output reg [DAC_DATA_WID-1:0] adjval
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);
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/**** Stage 1: Convert error to real value, calculate Δt = cycles/100MHz
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*
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* e_unscaled: ERR_WID.0
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* x INT_TO_REAL: 0.INT_TO_REAL_WID
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*- -----------------------------
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* e_scaled_unsat: ERR_WID + INT_TO_REAL_WID
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*/
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localparam ERR_WID = ADC_WID + 1;
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wire [ERR_WID-1:0] e_unscaled = setpt - measured;
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reg arm_stage_1 = 0;
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wire mul_scale_err_fin;
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localparam E_UNTRUNC_WID = ERR_WID + INT_TO_REAL_WID;
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wire [E_UNTRUNC_WID-1:0] e_scaled_unsat;
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boothmul #(
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.A1_LEN(INT_TO_REAL_WID),
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.A2_LEN(ERR_WID)
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) mul_scale_err (
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.clk(clk),
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.arm(arm_stage_1),
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.a1(INT_TO_REAL),
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.a2(e_unscaled),
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.outn(e_scaled_unsat),
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.fin(mul_scale_err_fin)
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);
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localparam E_WID = E_UNTRUNC_WID > CONSTS_WID ? CONSTS_WID : E_UNTRUNC_WID;
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wire [E_WID-1:0] e;
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localparam E_FRAC = E_WID < CONSTS_FRAC ? E_WID : E_WID - CONSTS_FRAC;
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localparam E_WHOLE = E_WID - E_FRAC;
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/* Don't bother keeping numbers larger than the constant width
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* since the value will always fit in it. */
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generate if (E_UNTRUNC_WID > CONSTS_WID) begin
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intsat #(
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.IN_LEN(E_UNTRUNC_WID),
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.LTRUNC(E_UNTRUNC_WID - CONSTS_WHOLE)
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) sat_mul_scale_err (
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.inp(e_scaled_unsat),
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.outp(e)
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);
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end else begin
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assign e = e_scaled_unsat;
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end endgenerate
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/* cycles: CYCLE_COUNT_WID.0
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* SEC_PER_CYCLE: 0....SEC_PER_CYCLE_WID
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* -x--------------------------------
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* dt_unsat: CYCLE_COUNT_WID + SEC_PER_CYCLE_WID
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*
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* Optimization note: the total width can be capped to below 1.
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*/
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localparam DT_UNSAT_WID = CYCLE_COUNT_WID + SEC_PER_CYCLE_WID;
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wire [DT_UNSAT_WID-1:0] dt_unsat;
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wire mul_dt_fin;
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boothmul #(
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.A1_LEN(CYCLE_COUNT_WID),
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.A2_LEN(SEC_PER_CYCLE_WID)
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) mul_dt (
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.clk(clk),
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.arm(arm_stage_1),
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.a1(cycles),
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.a2(SEC_PER_CYCLE),
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.outn(dt_unsat),
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.fin(mul_dt_fin)
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);
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localparam DT_WID = DT_UNSAT_WID > CONSTS_WID ? CONSTS_WID : DT_UNSAT_WID;
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wire [DT_WID-1:0] dt;
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localparam DT_WHOLE = DT_WID < CONSTS_FRAC ? 0 : CONSTS_FRAC - DT_WID;
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localparam DT_FRAC = DT_WID - DT_WHOLE;
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generate if (DT_UNSAT_WID > CONSTS_WID) begin
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intsat #(
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.IN_LEN(DT_UNSAT_WID),
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.LTRUNC(DT_UNSAT_WID - CONSTS_WID)
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) insat_dt (
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.inp(dt_unsat),
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.outp(dt)
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);
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end else begin
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assign dt = dt_unsat;
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end endgenerate
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/**** Stage 2: Calculate P + IΔt
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* I: CONSTS_WHOLE.CONSTS_FRAC
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* x dt: DT_WHOLE.DT_FRAC
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*-- -------------------------------
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* Idt_unscaled:
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*-- --------------------------------
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* Idt: CONSTS_WHOLE.CONSTS_FRAC
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*
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* Right-truncate DT_FRAC bits to ensure CONSTS_FRAC
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* Integer-sature the DT_WHOLE bits if it extends far enough
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*/
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wire stage2_finished;
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reg arm_stage2 = 0;
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wire [CONSTS_WID-1:0] idt;
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mul_const #(
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/* TODO: does this autoinfer CONSTS_WID? */
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.CONSTS_WHOLE(CONSTS_WHOLE),
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.CONSTS_FRAC(CONSTS_FRAC),
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.IN_WHOLE(DT_WHOLE),
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.IN_FRAC(DT_FRAC)
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) mul_const_idt (
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.clk(clk),
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.inp(dt),
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.const_in(cl_I),
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.arm(arm_stage2),
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.outp(idt),
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.finished(stage2_finished)
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);
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wire [CONSTS_WID:0] pidt_untrunc = cl_P + idt;
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/* Assuming that the constraints on cl_P, I, and dt hold */
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wire [CONSTS_WID-1:0] pidt = pidt_untrunc[CONSTS_WID-1:0];
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/**** Stage 3: calculate e_t(P + IΔt) and P e_{t-1} ****/
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reg arm_stage3 = 0;
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wire epidt_finished;
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wire pe_finished;
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wire [CONSTS_WID-1:0] epidt;
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mul_const #(
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.CONSTS_WHOLE(CONSTS_WHOLE),
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.CONSTS_FRAC(CONSTS_FRAC),
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.IN_WHOLE(E_WHOLE),
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.IN_FRAC(E_FRAC)
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) mul_const_epidt (
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.clk(clk),
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.inp(e),
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.const_in(idt),
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.arm(arm_stage3),
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.outp(epidt),
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.finished(epidt_finished)
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);
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wire [CONSTS_WID-1:0] pe;
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mul_const #(
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.COSNTS_WHOLE(CONSTS_WHOLE),
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.CONSTS_FRAC(CONSTS_FRAC),
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.IN_WHOLE(E_WHOLE),
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.IN_FRAC(E_FRAC)
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) mul_const_pe (
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.clk(clk),
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.inp(e),
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.const_in(idt),
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.arm(arm_stage3),
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.outp(pe),
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.finished(epidt_finished)
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);
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/******* State machine ********/
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localparam WAIT_ON_ARM = 0;
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localparam WAIT_ON_STAGE_1 = 1;
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localparam WAIT_ON_STAGE_2 = 2;
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localparam WAIT_ON_STAGE_3 = 3;
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localparam WAIT_ON_DISARM = 4;
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localparam STATE_SIZ = 3;
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reg [STATE_SIZ-1:0] state = WAIT_ON_ARM;
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always @ (posedge clk) begin
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case (state) begin
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WAIT_ON_ARM: begin
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if (arm) begin
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arm_stage_1 <= 1;
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state <= WAIT_ON_STAGE_1;
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end
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end
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WAIT_ON_STAGE_1: begin
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if (mul_scale_err_fin && mul_dt_fin) begin
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arm_stage_1 <= 0;
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arm_stage_2 <= 1;
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state <= WAIT_ON_STAGE_2;
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end
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end
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WAIT_ON_STAGE_2: begin
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if (stage2_finished) begin
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arm_stage_2 <= 0;
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arm_stage_3 <= 1;
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state <= WAIT_ON_STAGE_3;
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end
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end
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WAIT_ON_STAGE_3: begin
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if (epidt_finished && pe_finished) begin
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arm_stage3 <= 0;
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finished <= 1;
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state <= WAIT_ON_DISARM;
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end
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end
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WAIT_ON_DISARM: begin
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if (!arm) begin
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finished <= 0;
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state <= WAIT_ON_ARM;
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end
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end
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end
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endmodule
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@ -0,0 +1,56 @@
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module mul_const #(
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parameter CONSTS_WHOLE = 8,
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parameter CONSTS_FRAC = 40,
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parameter CONSTS_WID = CONSTS_WHOLE + CONSTS_FRAC,
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parameter IN_WHOLE = CONSTS_WHOLE,
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parameter IN_FRAC = CONSTS_FRAC,
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parameter IN_WID = IN_WHOLE + IN_FRAC
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) (
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input clk,
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input signed [IN_WID-1:0] inp,
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input signed [CONSTS_WID-1:0] const_in,
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input arm,
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output signed [CONSTS_WID-1:0] outp,
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output finished
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);
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localparam UNSAT_WID = CONSTS_WID + IN_WID;
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wire signed [UNSAT_WID-1:0] unsat;
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boothmul #(
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.A1_LEN(CONSTS_WID),
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.A2_LEN(IN_WID)
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) mul (
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.clk(clk),
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.arm(arm),
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.a1(const_in),
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.a2(inp),
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.outn(unsat),
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.fin(finished)
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);
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localparam RIGHTTRUNC_WID = UNSAT_WID - IN_FRAC;
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wire signed [RIGHTTRUNC_WID-1:0] rtrunc =
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unsat[UNSAT_WID-1:IN_FRAC];
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generate if (IN_WHOLE > 0) begin
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intsat #(
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.IN_LEN(RIGHTTRUNC_WID),
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.LTRUNC(IN_WHOLE)
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) sat (
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.inp(rtrunc),
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.outp(outp)
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);
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end else begin
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assign outp = rtrunc;
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end endgenerate
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`ifdef VERILATOR
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initial begin
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$dumpfile("mul_const.fst");
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$dumpvars();
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end
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`endif
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endmodule
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@ -0,0 +1,75 @@
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#include <cstdio>
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#include <cstdint>
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#include "Vmul_const.h"
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using ModType = Vmul_const;
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uint32_t main_time = 0;
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double sc_time_stamp() {
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return main_time;
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}
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ModType *mod;
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static void run_clock() {
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for (i = 0; i < 2; i++) {
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mod->clk = !mod->clk;
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mod->eval();
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main_time++;
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}
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}
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static void init(int argc, char **argv) {
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Verilator::commandArgs(argc, argv);
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Verilated::traceEverOn(true);
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mod = new ModType;
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mod->clk = 0;
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}
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#define BITMASK(n) ((1 << (n)) - 1)
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static void satmul(int64_t const_in, int64_t inp) {
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int64_t r = const_in * inp;
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if (r >= BITMASK(48))
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return BITMASK(48);
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else if (r <= -BITMASK(48))
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return -BITMASK(48);
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else
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return r;
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}
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#define RUNS 10000
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static void run(uint64_t const_in, uint64_t inp) {
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const_in &= BITMASK(48);
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inp &= BITMASK(IN_WID);
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mod->inp = inp;
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mod->const_in = const_in;
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mod->arm = 1;
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while (!mod->finished)
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run_clock();
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mod->finished = 0;
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run_clock();
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int64_t real_result = satmul(const_in, inp);
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if (real_result != outp) {
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printf("%llX * %llX = %llX (got %llX)\n",
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std::reinterpret_cast<uint64_t>(const_in),
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std::reinterpret_cast<uint64_t>(inp),
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std::reinterpret_cast<uint64_t>(real_result),
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std::reinterpret-cast<uint64_t>(outp));
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exit(1);
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}
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}
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int main(int argc, char **argv) {
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run_clock();
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for (int i = 0; i < RUNS; i++) {
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run(rand() - rand(), rand() - rand());
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}
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return 0;
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}
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