more work on linux upsilon
This commit is contained in:
parent
67b07516cf
commit
be03d68e6f
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@ -16,7 +16,6 @@ firmware/rtl/control_loop/control_loop_cmds.h
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firmware/rtl/raster/ram_shim_cmds.h
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firmware/rtl/raster/raster_cmds.h
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firmware/rtl/base/base.v
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firmware/rtl/control_loop/boothmul.v
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firmware/rtl/control_loop/control_loop.v
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firmware/rtl/control_loop/control_loop_cmds.vh
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firmware/rtl/control_loop/control_loop_math.v
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@ -6,14 +6,16 @@ all: rtl_codegen build/digilent_arty/digilent_arty.bit overlay.dts overlay.cmake
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rtl_codegen:
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cd rtl && make
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build/digilent_arty/digilent_arty.bit: soc.py
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csr.json build/digilent_arty/digilent_arty.bit: soc.py
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python3 soc.py
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clean:
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rm -rf build csr.json overlay.config overlay.dts pin_io.h
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rm -rf build csr.json overlay.config overlay.dts pin_io.h arty.dts arty.dtb
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cd rtl && make clean
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overlay.dts overlay.cmake: csr.json litex_json2dts_zephyr.py
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# NOTE: Broken in LiteX 2022.4.
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$(DEVICETREE_GEN_DIR)/litex_json2dts_zephyr.py --dts overlay.dts --config overlay.cmake csr.json
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arty.dts: csr.json
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litex_json2dts_linux.py csr.json > arty.dts
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arty.dtb: arty.dts
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dtc -O dtb -o arty.dtb arty.dts
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pin_io.c: csr.json generate_csr_locations.py
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python3 generate_csr_locations.py > pin_io.c
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@ -1,3 +1,4 @@
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##########################################################################
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# Portions of this file incorporate code licensed under the
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# BSD 2-Clause License.
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#
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@ -30,6 +31,7 @@
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# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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##########################################################################
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# There is nothing fundamental about the Arty A7(35|100)T to this
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# design, but another eval board will require some porting.
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@ -221,7 +223,7 @@ class _CRG(Module):
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if with_dram:
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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class CryoSNOM1SoC(SoCCore):
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class UpsilonSoC(SoCCore):
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def __init__(self, variant):
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sys_clk_freq = int(100e6)
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platform = board_spec.Platform(variant=variant, toolchain="f4pga")
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@ -291,7 +293,7 @@ class CryoSNOM1SoC(SoCCore):
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self.submodules.base = Base(ClockSignal(), self.sdram, platform)
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def main():
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soc = CryoSNOM1SoC("a7-100")
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soc =UpsilonSoC("a7-100")
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builder = Builder(soc, csr_json="csr.json", compile_software=True)
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builder.build()
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@ -1,30 +0,0 @@
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#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Dolu1990 <charles.papon.90@gmail.com>
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#
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# Compiler flags
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platform-cppflags-y =
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platform-cflags-y =
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platform-asflags-y =
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platform-ldflags-y =
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# Command for platform specific "make run"
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platform-runcmd = echo LiteX/VexRiscv SMP
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PLATFORM_RISCV_XLEN = 32
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PLATFORM_RISCV_ABI = ilp32
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PLATFORM_RISCV_ISA = rv32ima
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PLATFORM_RISCV_CODE_MODEL = medany
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# Blobs to build
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FW_TEXT_START=0x40F00000
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FW_DYNAMIC=y
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FW_JUMP=y
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FW_JUMP_ADDR=0x40000000
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FW_JUMP_FDT_ADDR=0x40EF0000
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FW_PAYLOAD=y
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FW_PAYLOAD_OFFSET=0x40000000
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FW_PAYLOAD_FDT_ADDR=0x40EF0000
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@ -1,67 +0,0 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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* Copyright (c) 2020 Dolu1990 <charles.papon.90@gmail.com>
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*
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*/
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#include <stdint.h>
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#define UART_EV_TX 0x1
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#define UART_EV_RX 0x2
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#define MMPTR(a) (*((volatile uint32_t *)(a)))
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static inline void csr_write_simple(unsigned long v, unsigned long a)
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{
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MMPTR(a) = v;
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}
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static inline unsigned long csr_read_simple(unsigned long a)
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{
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return MMPTR(a);
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}
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#define CSR_BASE 0xf0000000L
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static inline uint8_t uart_rxtx_read(void) {
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return csr_read_simple(CSR_BASE + 0x1000L);
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}
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static inline void uart_rxtx_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x1000L);
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}
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static inline uint8_t uart_txfull_read(void) {
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return csr_read_simple(CSR_BASE + 0x1004L);
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}
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static inline uint8_t uart_rxempty_read(void) {
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return csr_read_simple(CSR_BASE + 0x1008L);
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}
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static inline void uart_ev_pending_write(uint8_t v) {
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csr_write_simple(v, CSR_BASE + 0x1010L);
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}
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static inline uint8_t uart_txempty_read(void) {
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return csr_read_simple(CSR_BASE + 0x1018L);
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}
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static inline uint8_t uart_rxfull_read(void) {
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return csr_read_simple(CSR_BASE + 0x101cL);
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}
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void vex_putc(char c){
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while (uart_txfull_read());
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uart_rxtx_write(c);
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uart_ev_pending_write(UART_EV_TX);
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}
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int vex_getc(void){
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char c;
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if (uart_rxempty_read()) return -1;
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c = uart_rxtx_read();
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uart_ev_pending_write(UART_EV_RX);
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return c;
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}
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@ -11,55 +11,30 @@
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_platform.h>
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#include <sbi_utils/irqchip/plic.h>
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#include <sbi_utils/serial/uart8250.h>
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#include <sbi_utils/serial/litex_serial.h>
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#include <sbi_utils/sys/clint.h>
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/* clang-format off */
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#define VEX_HART_COUNT 8
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#define VEX_HART_COUNT 1
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#define VEX_PLATFORM_FEATURES (SBI_PLATFORM_HAS_TIMER_VALUE | SBI_PLATFORM_HAS_MFAULTS_DELEGATION)
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#define VEX_CLINT_ADDR 0xF0010000
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#define VEX_HART_STACK_SIZE 8192
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#define VEX_HART_STACK_SIZE SBI_PLATFORM_DEFAULT_STACK_SIZE
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/* clang-format on */
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static struct clint_data clint = {VEX_CLINT_ADDR, 0, VEX_HART_COUNT, true};
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static int vex_early_init(bool cold_boot)
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{
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return 0;
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}
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static int vex_final_init(bool cold_boot)
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{
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return 0;
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}
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static u32 vex_pmp_region_count(u32 hartid)
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{
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return 0;
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}
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static int vex_pmp_region_info(u32 hartid, u32 index, ulong *prot, ulong *addr,
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ulong *log2size)
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{
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int ret = 0;
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switch (index) {
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default:
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ret = -1;
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break;
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};
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return ret;
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}
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extern void vex_putc(char ch);
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extern int vex_getc(void);
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static int vex_console_init(void)
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{
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return 0;
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}
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static int vex_irqchip_init(bool cold_boot)
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{
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return 0;
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@ -90,41 +65,21 @@ static int vex_timer_init(bool cold_boot)
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return clint_warm_timer_init();
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}
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static int vex_system_reset(u32 type)
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{
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/* Tell the "finisher" that the simulation
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* was successful so that QEMU exits
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*/
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return 0;
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}
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const struct sbi_platform_operations platform_ops = {
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.pmp_region_count = vex_pmp_region_count,
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.pmp_region_info = vex_pmp_region_info,
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.final_init = vex_final_init,
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.console_putc = vex_putc,
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.console_getc = vex_getc,
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.console_init = vex_console_init,
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.irqchip_init = vex_irqchip_init,
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.ipi_send = clint_ipi_send,
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.ipi_clear = clint_ipi_clear,
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.ipi_init = vex_ipi_init,
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.timer_value = clint_timer_value,
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.timer_event_stop = clint_timer_event_stop,
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.timer_event_start = clint_timer_event_start,
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.timer_init = vex_timer_init,
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.system_reset = vex_system_reset
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.early_init = vex_early_init,
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.final_init = vex_final_init,
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.irqchip_init = vex_irqchip_init,
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.ipi_init = vex_ipi_init,
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.timer_init = vex_timer_init
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};
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const struct sbi_platform platform = {
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.opensbi_version = OPENSBI_VERSION,
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.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
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.name = "LiteX / VexRiscv-SMP",
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.features = VEX_PLATFORM_FEATURES,
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.hart_count = VEX_HART_COUNT,
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.hart_stack_size = VEX_HART_STACK_SIZE,
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.platform_ops_addr = (unsigned long)&platform_ops
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.opensbi_version = OPENSBI_VERSION,
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.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
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.name = "LiteX / VexRiscv",
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.features = VEX_PLATFORM_FEATURES,
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.hart_count = VEX_HART_COUNT,
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.hart_stack_size = VEX_HART_STACK_SIZE,
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.platform_ops_addr = (unsigned long)&platform_ops
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};
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