quick hack: pre-prepreprocess verilog files

.gitignore

@@ -19,3 +19,4 @@ firmware/rtl/control_loop/boothmul.v
 firmware/rtl/control_loop/control_loop.v
 firmware/rtl/control_loop/control_loop_cmds.vh
 firmware/rtl/control_loop/control_loop_math.v
+*_preprocessed.v

firmware/rtl/spi/Makefile

@@ -1,9 +1,16 @@
 # Makefile for tests and hardware verification.
 
-.PHONY: test clean
+.PHONY: test clean codegen
 
+all: test codegen
 test: obj_dir/Vspi_switch
 
+codegen: spi_master_ss_preprocessed.v spi_master_preprocessed.v \
+         spi_master_ss_no_write_preprocessed.v
+
+%_preprocessed.v: %.v
+	verilator -E $< > $@
+
 SRC= spi_switch.v spi_switch_sim.cpp
 obj_dir/Vspi_switch.mk: $(SRC)
 	verilator --cc --exe -Wall \

firmware/rtl/waveform/Makefile

@@ -1,9 +1,14 @@
 # Makefile for tests and hardware verification.
 
-.PHONY: test clean
+.PHONY: test clean codegen
 
+all: test codegen
 test: obj_dir/Vbram_interface_sim obj_dir/Vwaveform_sim
 
+codegen: bram_interface_preprocessed.v waveform_preprocessed.v
+%_preprocessed.v: %.v
+	verilator -E $< > $@
+
 bram_SRC= bram_interface_sim.v dma_sim.v bram_interface.v bram_interface_sim.cpp
 
 obj_dir/Vbram_interface_sim.mk: $(bram_SRC)

firmware/soc.py

@@ -302,17 +302,17 @@ class CryoSNOM1SoC(SoCCore):
 		sys_clk_freq = int(100e6)
 		platform = board_spec.Platform(variant=variant, toolchain="f4pga")
 		self.submodules.crg = _CRG(platform, sys_clk_freq, True)
-		platform.add_source("rtl/spi/spi_switch.v")
-		platform.add_source("rtl/spi/spi_master.v")
-		platform.add_source("rtl/spi/spi_master_ss.v")
-		platform.add_source("rtl/spi/spi_master_ss_no_write.v")
+		platform.add_source("rtl/spi/spi_switch_preprocessed.v")
+		platform.add_source("rtl/spi/spi_master_preprocessed.v")
+		platform.add_source("rtl/spi/spi_master_ss_preprocessed.v")
+		platform.add_source("rtl/spi/spi_master_ss_no_write_preprocessed.v")
 		platform.add_source("rtl/control_loop/sign_extend.v")
 		platform.add_source("rtl/control_loop/intsat.v")
 		platform.add_source("rtl/control_loop/boothmul.v")
 		platform.add_source("rtl/control_loop/control_loop_math.v")
 		platform.add_source("rtl/control_loop/control_loop.v")
-		platform.add_source("rtl/waveform/bram_interface.v")
-		platform.add_source("rtl/waveform/waveform.v")
+		platform.add_source("rtl/waveform/bram_interface_preprocessed.v")
+		platform.add_source("rtl/waveform/waveform_preprocessed.v")
 		platform.add_source("rtl/base/base.v")
 
 		# SoCCore does not have sane defaults (no integrated rom)
@@ -332,8 +332,7 @@ class CryoSNOM1SoC(SoCCore):
 				csr_address_width=14,
 				csr_paging=0x800,
 				csr_ordering="big",
-				timer_uptime = True)
-
+				timer_uptime = True)e
 		# This initializes the connection to the physical DRAM interface.
 		self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
 			memtype		= "DDR3",