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quick hack: pre-prepreprocess verilog files

This commit is contained in:
Peter McGoron 2023-03-15 18:47:20 +00:00
parent ef8ce874ba
commit ca8078f9d6
4 changed files with 22 additions and 10 deletions
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1
.gitignore vendored
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@ -19,3 +19,4 @@ firmware/rtl/control_loop/boothmul.v
firmware/rtl/control_loop/control_loop.v firmware/rtl/control_loop/control_loop.v
firmware/rtl/control_loop/control_loop_cmds.vh firmware/rtl/control_loop/control_loop_cmds.vh
firmware/rtl/control_loop/control_loop_math.v firmware/rtl/control_loop/control_loop_math.v
*_preprocessed.v

9
firmware/rtl/spi/Makefile
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@ -1,9 +1,16 @@
# Makefile for tests and hardware verification. # Makefile for tests and hardware verification.
.PHONY: test clean .PHONY: test clean codegen
all: test codegen
test: obj_dir/Vspi_switch test: obj_dir/Vspi_switch
codegen: spi_master_ss_preprocessed.v spi_master_preprocessed.v \
spi_master_ss_no_write_preprocessed.v
%_preprocessed.v: %.v
verilator -E $< > $@
SRC= spi_switch.v spi_switch_sim.cpp SRC= spi_switch.v spi_switch_sim.cpp
obj_dir/Vspi_switch.mk: $(SRC) obj_dir/Vspi_switch.mk: $(SRC)
verilator --cc --exe -Wall \ verilator --cc --exe -Wall \

7
firmware/rtl/waveform/Makefile
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@ -1,9 +1,14 @@
# Makefile for tests and hardware verification. # Makefile for tests and hardware verification.
.PHONY: test clean .PHONY: test clean codegen
all: test codegen
test: obj_dir/Vbram_interface_sim obj_dir/Vwaveform_sim test: obj_dir/Vbram_interface_sim obj_dir/Vwaveform_sim
codegen: bram_interface_preprocessed.v waveform_preprocessed.v
%_preprocessed.v: %.v
verilator -E $< > $@
bram_SRC= bram_interface_sim.v dma_sim.v bram_interface.v bram_interface_sim.cpp bram_SRC= bram_interface_sim.v dma_sim.v bram_interface.v bram_interface_sim.cpp
obj_dir/Vbram_interface_sim.mk: $(bram_SRC) obj_dir/Vbram_interface_sim.mk: $(bram_SRC)

15
firmware/soc.py
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@ -302,17 +302,17 @@ class CryoSNOM1SoC(SoCCore):
sys_clk_freq = int(100e6) sys_clk_freq = int(100e6)
platform = board_spec.Platform(variant=variant, toolchain="f4pga") platform = board_spec.Platform(variant=variant, toolchain="f4pga")
self.submodules.crg = _CRG(platform, sys_clk_freq, True) self.submodules.crg = _CRG(platform, sys_clk_freq, True)
platform.add_source("rtl/spi/spi_switch.v") platform.add_source("rtl/spi/spi_switch_preprocessed.v")
platform.add_source("rtl/spi/spi_master.v") platform.add_source("rtl/spi/spi_master_preprocessed.v")
platform.add_source("rtl/spi/spi_master_ss.v") platform.add_source("rtl/spi/spi_master_ss_preprocessed.v")
platform.add_source("rtl/spi/spi_master_ss_no_write.v") platform.add_source("rtl/spi/spi_master_ss_no_write_preprocessed.v")
platform.add_source("rtl/control_loop/sign_extend.v") platform.add_source("rtl/control_loop/sign_extend.v")
platform.add_source("rtl/control_loop/intsat.v") platform.add_source("rtl/control_loop/intsat.v")
platform.add_source("rtl/control_loop/boothmul.v") platform.add_source("rtl/control_loop/boothmul.v")
platform.add_source("rtl/control_loop/control_loop_math.v") platform.add_source("rtl/control_loop/control_loop_math.v")
platform.add_source("rtl/control_loop/control_loop.v") platform.add_source("rtl/control_loop/control_loop.v")
platform.add_source("rtl/waveform/bram_interface.v") platform.add_source("rtl/waveform/bram_interface_preprocessed.v")
platform.add_source("rtl/waveform/waveform.v") platform.add_source("rtl/waveform/waveform_preprocessed.v")
platform.add_source("rtl/base/base.v") platform.add_source("rtl/base/base.v")
# SoCCore does not have sane defaults (no integrated rom) # SoCCore does not have sane defaults (no integrated rom)
@ -332,8 +332,7 @@ class CryoSNOM1SoC(SoCCore):
csr_address_width=14, csr_address_width=14,
csr_paging=0x800, csr_paging=0x800,
csr_ordering="big", csr_ordering="big",
timer_uptime = True) timer_uptime = True)e
# This initializes the connection to the physical DRAM interface. # This initializes the connection to the physical DRAM interface.
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3", memtype = "DDR3",