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fix adc_sim

This commit is contained in:
Peter McGoron 2022-11-21 22:04:46 -05:00
parent 5909f548d5
commit cfb0f92528
3 changed files with 3 additions and 2 deletions
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2
firmware/rtl/control_loop/adc_sim.v
View File

@ -39,8 +39,8 @@ always @ (posedge clk) begin
data <= indat;
fulfilled_raised <= 1;
request <= 0;
end else if (ss_raised && request && !fulfilled && fulfilled_raised) begin
rdy <= 1;
end else if (ss_raised && !fulfilled && fulfilled_raised) begin
fulfilled_raised <= 0;
ss_buf_L <= 0;
end else if (spi_fin) begin

2
firmware/rtl/control_loop/control_loop.v
View File

@ -226,7 +226,7 @@ reg [DELAY_WID-1:0] timer = 0;
/**** Timing. ****/
always @ (posedge clk) begin
if (state == CYCLE_START) begin
if (state == CYCLE_START && timer == 0) begin
counting_timer <= 1;
last_timer <= counting_timer;
end else begin

1
firmware/rtl/control_loop/control_loop_sim.cpp
View File

@ -56,6 +56,7 @@ int main(int argc, char **argv) {
set_value(0b11010111000010100011110101110000101000111, CONTROL_LOOP_P);
set_value((V)12 << CONSTS_FRAC, CONTROL_LOOP_I);
set_value(20, CONTROL_LOOP_DELAY);
set_value(10000, CONTROL_LOOP_SETPT);
set_value(1, CONTROL_LOOP_STATUS);
for (int tick = 0; tick < 10000; tick++) {