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add ram_fifo_dual_port wrapper to single port FIFO

This commit is contained in:
Peter McGoron 2022-12-17 10:03:06 -05:00
parent 3612148ee1
commit f0f1750a9a
2 changed files with 67 additions and 37 deletions
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52
firmware/rtl/raster/ram_fifo.v
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@ -1,52 +1,30 @@
/* YOSYS has a difficult time infering single port BRAM. It can infer
* double-port block ram, however. This module is written as a double
* port block ram, even though both clocks will end up being the same.
* TODO:
* "empty" and "full" status indiciators for simulation
* https://stackoverflow.com/questions/62703942/trouble-getting-yosys-to-infer-block-ram-array-rather-than-using-logic-cells-v
* The answer by "TinLethax" infers a BRAM.
*/
module ram_fifo #( module ram_fifo #(
parameter DAT_WID = 24, parameter DAT_WID = 24,
parameter FIFO_DEPTH = 1500, parameter FIFO_DEPTH = 1500,
parameter FIFO_DEPTH_WID = 11 parameter FIFO_DEPTH_WID = 11
) ( ) (
input RCLK, input clk,
input WCLK,
input rst, input rst,
input read_enable, input read_enable,
input write_enable, input write_enable,
input signed [DAT_WID-1:0] write_dat, input signed [DAT_WID-1:0] write_dat,
output reg signed [DAT_WID-1:0] read_dat output signed [DAT_WID-1:0] read_dat
); );
reg [DAT_WID-1:0] memory [FIFO_DEPTH-1:0]; ram_fifo_dual_port #(
initial memory[0] <= 24'b0; .DAT_WID(DAT_WID),
.FIFO_DEPTH(FIFO_DEPTH),
/* Read domain */ .FIFO_DEPTH_WID(FIFO_DEPTH_WID)
) m (
reg [FIFO_DEPTH_WID-1:0] read_ptr = 0; .WCLK(clk),
always @ (posedge RCLK) begin .RCLK(clk),
if (rst) begin .rst(rst),
read_ptr <= 0; .read_enable(read_enable),
end else if (read_enable) begin .write_enable(write_enable),
read_dat <= memory[read_ptr]; .write_dat(write_dat),
read_ptr <= read_ptr + 1; .read_dat(read_dat)
end );
end
/* Write domain */
reg [FIFO_DEPTH_WID-1:0] write_ptr = 0;
always @ (posedge WCLK) begin
if (rst) begin
write_ptr <= 0;
end else if (write_enable) begin
memory[write_ptr] <= write_dat;
write_ptr <= write_ptr + 1;
end
end
endmodule endmodule

52
firmware/rtl/raster/ram_fifo_dual_port.v Normal file
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@ -0,0 +1,52 @@
/* YOSYS has a difficult time infering single port BRAM. It can infer
* double-port block ram, however. This module is written as a double
* port block ram, even though both clocks will end up being the same.
* TODO:
* "empty" and "full" status indiciators for simulation
* https://stackoverflow.com/questions/62703942/trouble-getting-yosys-to-infer-block-ram-array-rather-than-using-logic-cells-v
* The answer by "TinLethax" infers a BRAM.
*/
module ram_fifo_dual_port #(
parameter DAT_WID = 24,
parameter FIFO_DEPTH = 1500,
parameter FIFO_DEPTH_WID = 11
) (
input RCLK,
input WCLK,
input rst,
input read_enable,
input write_enable,
input signed [DAT_WID-1:0] write_dat,
output reg signed [DAT_WID-1:0] read_dat
);
reg [DAT_WID-1:0] memory [FIFO_DEPTH-1:0];
initial memory[0] <= 24'b0;
/* Read domain */
reg [FIFO_DEPTH_WID-1:0] read_ptr = 0;
always @ (posedge RCLK) begin
if (rst) begin
read_ptr <= 0;
end else if (read_enable) begin
read_dat <= memory[read_ptr];
read_ptr <= read_ptr + 1;
end
end
/* Write domain */
reg [FIFO_DEPTH_WID-1:0] write_ptr = 0;
always @ (posedge WCLK) begin
if (rst) begin
write_ptr <= 0;
end else if (write_enable) begin
memory[write_ptr] <= write_dat;
write_ptr <= write_ptr + 1;
end
end
endmodule