 Peter McGoron
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c42e2fe419
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add write-read interface to control loop
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2022-10-18 07:10:06 -04:00 |
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Peter McGoron
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dc2b1fe339
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move SPI master out of control loop design
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2022-10-17 14:37:37 -04:00 |
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Peter McGoron
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0ef00c15d7
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move simulators to the same directory of the simulated core
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2022-10-17 00:45:19 -04:00 |
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Peter McGoron
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029cc53c5f
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some more changes
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2022-10-17 00:44:30 -04:00 |
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Peter McGoron
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5125719a1f
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move control loop stub code to control loop rtl
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2022-10-12 08:48:34 -04:00 |
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Peter McGoron
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0298299402
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add everything im working on
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2022-09-16 18:01:34 -04:00 |
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Peter McGoron
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01cbcb5fae
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add verilog SPI
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2022-07-21 17:07:52 -04:00 |