1. Add a new Upsilon MicroPython standard library in the linux/
subdirectory. This puts all the submodules into classes with methods
for ease of access.
2. Totally rewrite mmio.py code generation. Instead of just dumping
registers, the build system now instantiates classes which
encapsulate the module in question.
3. Split the PicoRV32 special register interface away from the PicoRV32.
It is now the PeekPokeInterface, which will be used in the future to
implement register control for Waveform and SPI.
4. Integrate Waveform into the design. Has not been tested yet.
New master buses can be added to PreemptiveInterface throughout the
code, simplifying the main SoC code. This removes the requirement that
the amount of masters to the interface needs to be known at
instantiation time.
1. Started writing a lot of documentation on how Upsilon is
structured. This will replace the very outdated documentation.
2. Fixed parameter access and writing. This is also a more generic
interface that can be used for Pico CPUs that implement different
routines.
1. Update LiteX to 2023.12. This update adds wishbone bus addressing
modes. Before this update, all wishbone buses used word addressing.
For example, 0x0 mapped to word 0, 0x0 mapped to word 1, etc. This
caused problems with the PicoRV32 and other modules, which are byte
addressed.
2. Use adapter to convert between byte and word addressing. The SRAM is
word addressed. The PicoRV32 shifts the address down by two bits to
address the correct word. The PicoRV32 core seems to expect this.
3. Add debug register output. This is not working yet.
4. Use LiteX PicoRV32 wishbone adapter instead of PicoRV32 default. This
seems to be simpler (combinatorial not synchronous).
5. Add some documentation.
6. Seperate config to new config file.
Peter McGoron