6 Commits

Author	SHA1	Message	Date
Peter McGoron	5909f548d5	control loop simulator passes lint	2022-11-21 21:41:50 -05:00
Peter McGoron	82ff659a44	add DAC ramp	2022-11-17 17:32:32 -05:00
Peter McGoron	0907a76c22	import spi v0.2	2022-11-14 08:43:16 -05:00
Peter McGoron	029cc53c5f	some more changes	2022-10-17 00:44:30 -04:00
Peter McGoron	0298299402	add everything im working on	2022-09-16 18:01:34 -04:00
Peter McGoron	01cbcb5fae	add verilog SPI	2022-07-21 17:07:52 -04:00