5 Commits

Author	SHA1	Message	Date
Peter McGoron	15b8fcbe7e	reset pins and test clock	2023-05-10 14:35:57 -04:00
Peter McGoron	33ec8351d8	correctly (and crudely) simulate control loop ... Issue was that the ADC cycle half wait (SCK delay) was too fast for the input buffering (since MISO and MOSI are physical inputs and not FPGA wires).	2022-11-24 09:48:19 -05:00
Peter McGoron	5909f548d5	control loop simulator passes lint	2022-11-21 21:41:50 -05:00
Peter McGoron	0907a76c22	import spi v0.2	2022-11-14 08:43:16 -05:00
Peter McGoron	029cc53c5f	some more changes	2022-10-17 00:44:30 -04:00