77 lines
1.6 KiB
Verilog
77 lines
1.6 KiB
Verilog
/* Copyright 2023 (C) Peter McGoron
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* This file is a part of Upsilon, a free and open source software project.
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* For license terms, refer to the files in `doc/copying` in the Upsilon
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* source distribution.
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*/
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/* Implements a synchronous(!) FIFO using inferred Block RAM. This
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* must wrap "ram_fifo_dual_port" due to difficulties YOSYS has with
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* inferring Block RAM: refer to that module for details.
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*/
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`timescale 10ns/10ns
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module ram_fifo #(
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parameter DAT_WID = 24,
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parameter FIFO_DEPTH_WID = 11,
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parameter [FIFO_DEPTH_WID-1:0] FIFO_DEPTH = 1500
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) (
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input clk,
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input rst,
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input read_enable,
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input write_enable,
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input signed [DAT_WID-1:0] write_dat,
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output signed [DAT_WID-1:0] read_dat,
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output empty,
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output full
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);
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reg [FIFO_DEPTH_WID-1:0] fifo_size;
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initial fifo_size = 0;
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assign empty = fifo_size == 0;
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assign full = fifo_size == FIFO_DEPTH;
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ram_fifo_dual_port #(
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.DAT_WID(DAT_WID),
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.FIFO_DEPTH(FIFO_DEPTH),
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.FIFO_DEPTH_WID(FIFO_DEPTH_WID)
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) m (
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.WCLK(clk),
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.RCLK(clk),
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.rst(rst),
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.read_enable(read_enable),
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.write_enable(write_enable),
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.write_dat(write_dat),
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.read_dat(read_dat)
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);
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always @ (posedge clk) begin
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if (rst) begin
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fifo_size <= 0;
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end else if (read_enable && !write_enable) begin
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fifo_size <= fifo_size - 1;
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`ifdef VERILATOR
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if (fifo_size == 0) begin
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$error("fifo underflow");
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end
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`endif
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end else if (write_enable && !read_enable) begin
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fifo_size <= fifo_size + 1;
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`ifdef VERILATOR
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if (fifo_size == FIFO_DEPTH) begin
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$error("fifo overflow");
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end
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`endif
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end
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end
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/*
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`ifdef VERILATOR
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initial begin
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$dumpfile("ram_fifo.vcd");
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$dumpvars;
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end
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`endif
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*/
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endmodule
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