289 lines
11 KiB
Python
289 lines
11 KiB
Python
# Copyright 2023-2024 (C) Peter McGoron
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#
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# This file is a part of Upsilon, a free and open source software project.
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# For license terms, refer to the files in `doc/copying` in the Upsilon
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# source distribution.
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# XXX: PicoRV32 code only handles word-sized registers correctly. Memory
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# registers made up of multiple words are not supported right now.
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from migen import *
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from litex.soc.interconnect.csr import CSRStorage, CSRStatus
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from litex.soc.interconnect.wishbone import Interface, SRAM, Decoder
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from litex.gen import LiteXModule
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from region import *
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class PreemptiveInterface(LiteXModule):
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""" A preemptive interface is a manually controlled Wishbone interface
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that stands between multiple masters (potentially interconnects) and a
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single slave. A master controls which master (or interconnect) has access
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to the slave. This is to avoid bus contention by having multiple buses.
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To use this module, instantiate it. Then connect the controlling master
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to ``self.buses[0]``. Connect the other masters to ``self.buses[1]``, etc.
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Since the buses are seperate, origins don't have to be the same, but the
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size of the region will be the same as the slave interface.
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"""
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def __init__(self, slave_bus, addressing="word", name=None):
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"""
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:param slave_bus: Instance of Wishbone.Interface that connects to the
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slave's bus.
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:param addressing: Addressing style of the slave. Default is "word". Note
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that masters may have to convert when selecting self.buses. This conversion
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is not done in this module.
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:param name: Name for debugging purposes.
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"""
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self.slave_bus = slave_bus
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self.addressing=addressing
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self.buses = []
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self.name = name
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self.master_names = []
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self.pre_finalize_done = False
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def add_master(self, name):
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""" Adds a new master bus to the PI.
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:return: The interface to the bus.
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:param name: Name associated with this master.
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"""
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if self.pre_finalize_done:
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raise Exception(self.name + ": Attempted to modify PreemptiveInterface after pre-finalize")
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self.master_names.append(name)
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iface = Interface(data_width=32, address_width=32, addressing=self.addressing)
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self.buses.append(iface)
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return iface
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def pre_finalize(self, dump_name):
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# NOTE: DUMB HACK! CSR bus logic is NOT generated when inserted at do_finalize time!
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if self.pre_finalize_done:
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raise Exception(self.name + ": Cannot pre-finalize twice")
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self.pre_finalize_done = True
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masters_len = len(self.buses)
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if masters_len > 1:
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self.master_select = CSRStorage(masters_len, name='master_select', description='RW bitstring of which master interconnect to connect to')
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# FIXME: Implement PreemptiveInterfaceController module to limit proliferation
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# of JSON files
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with open(dump_name, 'wt') as f:
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import json
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json.dump(self.master_names, f)
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def do_finalize(self):
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if not self.pre_finalize_done:
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raise Exception(self.name + ": PreemptiveInterface needs a manual call to pre_finalize()")
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masters_len = len(self.buses)
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if masters_len == 0:
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return None
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"""
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Construct a combinatorial case statement. In verilog, the case
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statment would look like
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always @ (*) case (master_select)
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1: begin
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// Assign slave to master 1,
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// Assign all other masters to dummy ports
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end
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2: begin
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// Assign slave to master 2,
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// Assign all other masters to dummy ports
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end
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// more cases:
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default: begin
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// assign slave to master 0
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// Assign all other masters to dummy ports
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end
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Case statement is a dictionary, where each key is either the
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number to match or "default", which is the default case.
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Avoiding latches:
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Left hand sign (assignment) is always an input.
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"""
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def assign_for_case(current_case):
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asn = [ ]
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for j in range(masters_len):
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if current_case == j:
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""" Assign all inputs (for example, slave reads addr
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from master) to outputs. """
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asn += [
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self.slave_bus.adr.eq(self.buses[j].adr),
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self.slave_bus.dat_w.eq(self.buses[j].dat_w),
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self.slave_bus.cyc.eq(self.buses[j].cyc),
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self.slave_bus.stb.eq(self.buses[j].stb),
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self.slave_bus.we.eq(self.buses[j].we),
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self.slave_bus.sel.eq(self.buses[j].sel),
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self.buses[j].dat_r.eq(self.slave_bus.dat_r),
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self.buses[j].ack.eq(self.slave_bus.ack),
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]
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else:
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""" Master bus will always read 0 when they are not
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selected, and writes are ignored. They will still
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get a response to avoid timeouts. """
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asn += [
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self.buses[j].dat_r.eq(0),
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self.buses[j].ack.eq(self.buses[j].cyc & self.buses[j].stb),
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]
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return asn
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cases = {"default": assign_for_case(0)}
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# This loop only executes cases when there is more than one master.
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for i in range(1, masters_len):
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cases[i] = assign_for_case(i)
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# If there is only one case, just connect the two interfaces as usual.
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if masters_len == 1:
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self.comb += cases["default"]
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else:
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self.comb += Case(self.master_select.storage, cases)
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def gen_pico_header(pico_name):
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""" Generate PicoRV32 C header for this CPU from JSON file. """
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import json
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with open(pico_name + "_mmio.h", "wt") as out:
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print('#pragma once', file=out)
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with open(pico_name + ".json") as f:
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js = json.load(f)
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for region in js:
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if js[region]["registers"] is None:
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continue
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origin = js[region]["origin"]
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for reg in js[region]["registers"]:
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macname = f"{region}_{reg}".upper()
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loc = origin + js[region]["registers"][reg]["origin"]
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print(f"#define {macname} (volatile uint32_t *)({loc})", file=out)
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# Parts of this class come from LiteX.
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#
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# Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2018 Sergiusz Bazanski <q3k@q3k.org>
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# Copyright (c) 2019 Antmicro <www.antmicro.com>
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# Copyright (c) 2019 Tim 'mithro' Ansell <me@mith.ro>
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# Copyright (c) 2018 William D. Jones <thor0505@comcast.net>
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# SPDX-License-Identifier: BSD-2-Clause
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class PicoRV32(LiteXModule):
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def add_cl_params(self):
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""" Add parameter region for control loop variables. Dumps the
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region information to a JSON file `dumpname`.
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"""
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self.params.add_register("cl_I", "1", 32)
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self.params.add_register("cl_P", "1", 32)
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self.params.add_register("deltaT", "1", 32)
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self.params.add_register("setpt", "1", 32)
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self.params.add_register("zset", "2", 32)
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self.params.add_register("zpos", "2", 32)
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def __init__(self, name, start_addr=0x10000, irq_addr=0x10010, stackaddr=0x100FF, param_origin=0x100000):
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self.name = name
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self.masterbus = Interface(data_width=32, address_width=32, addressing="byte")
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self.mmap = MemoryMap(self.masterbus)
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self.params = PeekPokeInterface()
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self.param_origin = param_origin
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self.params.add_register("enable", "1", 1)
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self.params.add_register("trap", "", 8)
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self.params.add_register("debug_adr", "", 32)
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self.params.add_register("dat_w", "", 32)
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self.params.add_register("pc", "", 32)
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self.params.add_register("opcode", "", 32)
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reg_args = {}
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for num, reg in enumerate(["ra", "sp", "gp", "tp", "t0", "t1", "t2",
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"s0_fp", "s1", "a0",
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"a1", "a2", "a3", "a4", "a5", "a6", "a7",
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"s2", "s3", "s4", "s5", "s6", "s7", "t3",
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"t4", "t5", "t6",], start=1):
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self.params.add_register(reg, "", 32)
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reg_args[f"o_dbg_reg_x{num}"] = self.params.signals[reg]
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mem_valid = Signal()
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mem_instr = Signal()
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mem_ready = Signal()
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mem_addr = Signal(32)
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mem_wdata = Signal(32)
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mem_wstrb = Signal(4)
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mem_rdata = Signal(32)
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self.comb += [
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self.masterbus.adr.eq(mem_addr),
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self.masterbus.dat_w.eq(mem_wdata),
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self.masterbus.we.eq(mem_wstrb != 0),
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self.masterbus.sel.eq(mem_wstrb),
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self.masterbus.cyc.eq(mem_valid),
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self.masterbus.stb.eq(mem_valid),
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self.masterbus.cti.eq(0),
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self.masterbus.bte.eq(0),
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mem_ready.eq(self.masterbus.ack),
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mem_rdata.eq(self.masterbus.dat_r),
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self.params.signals["debug_adr"].eq(mem_addr),
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self.params.signals["dat_w"].eq(mem_wdata),
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]
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self.specials += Instance("picorv32",
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p_COMPRESSED_ISA = 1,
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p_ENABLE_MUL = 1,
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p_REGS_INIT_ZERO = 1,
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p_PROGADDR_RESET=start_addr,
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p_PROGADDR_IRQ =irq_addr,
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p_STACKADDR = stackaddr,
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o_trap = self.params.signals["trap"],
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o_mem_valid = mem_valid,
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o_mem_instr = mem_instr,
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i_mem_ready = mem_ready,
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o_mem_addr = mem_addr,
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o_mem_wdata = mem_wdata,
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o_mem_wstrb = mem_wstrb,
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i_mem_rdata = mem_rdata,
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i_clk = ClockSignal(),
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i_resetn = self.params.signals["enable"],
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o_mem_la_read = Signal(),
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o_mem_la_write = Signal(),
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o_mem_la_addr = Signal(32),
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o_mem_la_wdata = Signal(32),
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o_mem_la_wstrb = Signal(4),
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o_pcpi_valid = Signal(),
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o_pcpi_insn = Signal(32),
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o_pcpi_rs1 = Signal(32),
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o_pcpi_rs2 = Signal(32),
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i_pcpi_wr = 0,
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i_pcpi_wait = 0,
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i_pcpi_rd = 0,
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i_pcpi_ready = 0,
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i_irq = 0,
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o_eoi = Signal(32),
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o_trace_valid = Signal(),
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o_trace_data = Signal(36),
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o_dbg_insn_addr = self.params.signals["pc"],
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o_dbg_insn_opcode = self.params.signals["opcode"],
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**reg_args
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)
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def do_finalize(self):
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self.mmap.finalize()
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self.mmap.dump_mmap(self.name + ".json")
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gen_pico_header(self.name)
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