10 lines
363 B
Verilog
10 lines
363 B
Verilog
/* Copyright 2023 (C) Peter McGoron
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* This file is a part of Upsilon, a free and open source software project.
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* For license terms, refer to the files in `doc/copying` in the Upsilon
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* source distribution.
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*/
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`define SPI_MASTER_SS_NAME spi_master_ss
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`define SPI_MASTER_NAME spi_master
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/* verilator lint_off DECLFILENAME */
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`include "spi_master_ss_template.v"
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