Peter McGoron 0a435f6dc8 rename control loop verilog simulation top level module to more descriptive name		2022-10-22 01:58:37 -04:00
..
rtl	rename control loop verilog simulation top level module to more descriptive name	2022-10-22 01:58:37 -04:00
A7-constraints.xdc	cleanup	2022-07-12 13:30:28 -04:00
COPYING	soc.py legal	2022-09-17 00:58:15 -04:00
Makefile	Makefiles depend on generated files	2022-07-13 14:11:56 -04:00
generate_csr_locations.py	change CSR types	2022-07-27 09:32:49 -04:00
soc.py	soc.py legal	2022-09-17 00:58:15 -04:00