Peter McGoron 0c10dc921c more work on control_loop ... * Make SPI masters internal to control loop module * Rename commands to use I isntead of alpha * add ADC value -> DAC value conversion to control loop math		2022-11-18 19:11:56 -05:00
..
rtl	more work on control_loop	2022-11-18 19:11:56 -05:00
A7-constraints.xdc	cleanup	2022-07-12 13:30:28 -04:00
COPYING	clarify licenses	2022-10-27 17:55:57 -04:00
Makefile	Makefiles depend on generated files	2022-07-13 14:11:56 -04:00
generate_csr_locations.py	change CSR types	2022-07-27 09:32:49 -04:00
soc.py	soc.py legal	2022-09-17 00:58:15 -04:00