15 lines
554 B
Markdown
15 lines
554 B
Markdown
This document is for recording notes on measurements done on Upslion
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running on actual FPGAs.
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Commit: `9c2731ad8d794d0b3c46999a40f0064f2b020c69`
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FPGA: Arty A7-100T
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F4PGA commit: `f43bb728b1bd9ef3807ef65bcf6b6629e0fa71f5`
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ADCs:
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SPI clocks take about 10ns to start going up and down from low voltage. They
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rise to about 500mV in that time. MISO oscillates up and down up to 50mV with
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no data present, rising and stays at that until it oscillates down. Should not
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be a problem. Probably capacitance/crosstalk. Ringing of about 40mV on clock
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and SS.
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