Peter McGoron 15480f11da ram_fifo: add empty and full ports		2022-12-18 06:06:44 +00:00
..
control_loop	control_loop: remove reg keyword, yosys doesnt like it	2022-12-17 09:56:26 -05:00
raster	ram_fifo: add empty and full ports	2022-12-18 06:06:44 +00:00
spi	correctly (and crudely) simulate control loop	2022-11-24 09:48:19 -05:00