Peter McGoron 1be89f314c simulate and verify ram_fifo and ram_fifo_dual_port		2022-12-17 18:39:58 +00:00
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control_loop	control_loop: remove reg keyword, yosys doesnt like it	2022-12-17 09:56:26 -05:00
raster	simulate and verify ram_fifo and ram_fifo_dual_port	2022-12-17 18:39:58 +00:00
spi	correctly (and crudely) simulate control loop	2022-11-24 09:48:19 -05:00