348 lines
12 KiB
Python
348 lines
12 KiB
Python
# Copyright 2023-2024 (C) Peter McGoron
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#
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# This file is a part of Upsilon, a free and open source software project.
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# For license terms, refer to the files in `doc/copying` in the Upsilon
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# source distribution.
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from migen import *
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from litex.soc.interconnect.wishbone import Interface
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from util import *
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from region import *
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class Waveform(LiteXModule):
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""" A Wishbone bus master that sends a waveform to a SPI master
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by reading from RAM. """
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public_registers = {
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"run" : Register(
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origin=0,
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bitwidth=1,
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rw=True,
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),
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"cntr": Register(
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origin=0x4,
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bitwidth=16,
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rw=False,
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),
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"do_loop": Register(
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origin=0x8,
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bitwidth= 1,
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rw= True,
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),
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"finished_or_ready": Register(
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origin=0xC,
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bitwidth= 2,
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rw= False,
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),
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"wform_width": Register(
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origin=0x10,
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bitwidth=16,
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rw= True,
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),
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"timer": Register(
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origin=0x14,
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bitwidth= 16,
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rw= False,
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),
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"timer_spacing": Register(
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origin= 0x18,
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bitwidth= 16,
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rw= True,
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)
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}
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width = 0x20
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def mmio(self, origin):
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r = ""
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for name, reg in self.public_registers.items():
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r += f'{name} = Register(loc={origin + reg.origin}, bitwidth={reg.bitwidth}, rw={reg.rw}),'
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return r
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def __init__(self,
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ram_start_addr = 0,
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spi_start_addr = 0x10000000,
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counter_max_wid = 16,
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timer_wid = 16,
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):
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# This is Waveform's bus to control SPI and RAM devices it owns.
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self.masterbus = Interface(address_width=32, data_width=32, addressing="byte")
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# This is the Waveform's interface that is controlled by the Main CPU.
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self.slavebus = b = Interface(address_width=32, data_width=32, addressing="byte")
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self.mmap = MemoryMap(self.masterbus)
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self.mmap.add_region("ram",
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BasicRegion(ram_start_addr, None))
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self.mmap.add_region("spi",
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BasicRegion(spi_start_addr, None))
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run = Signal()
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cntr = Signal(counter_max_wid)
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do_loop = Signal()
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ready = Signal()
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finished = Signal()
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wform_size = Signal(counter_max_wid)
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timer = Signal(timer_wid)
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timer_spacing = Signal(timer_wid)
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self.sync += If(b.cyc & b.stb & ~b.ack,
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Case(b.adr, {
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0x0: If(b.we,
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run.eq(b.dat_w[0]),
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).Else(
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b.dat_r[0].eq(run)
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),
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0x4: [
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b.dat_r[0:counter_max_wid].eq(cntr),
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],
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0x8: [
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If(b.we,
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do_loop.eq(b.dat_w[0]),
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).Else(
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b.dat_r[0].eq(do_loop),
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)
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],
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0xC: [
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b.dat_r[0].eq(ready),
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b.dat_r[1].eq(finished),
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],
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0x10: If(b.we,
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wform_size.eq(b.dat_w[0:counter_max_wid]),
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).Else(
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b.dat_r[0:counter_max_wid].eq(wform_size)
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),
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0x14: b.dat_r[0:timer_wid].eq(timer),
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0x18: If(b.we,
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timer_spacing.eq(b.dat_w[0:timer_wid]),
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).Else(
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b.dat_r[0:timer_wid].eq(timer_spacing),
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),
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# (W)A(V)EFO(RM)
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"default": b.dat_r.eq(0xAEF0AEF0),
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}
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),
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b.ack.eq(1),
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).Elif(~b.cyc,
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b.ack.eq(0),
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)
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self.specials += Instance("waveform",
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p_RAM_START_ADDR = ram_start_addr,
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p_SPI_START_ADDR = spi_start_addr,
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p_COUNTER_MAX_WID = counter_max_wid,
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p_TIMER_WID = timer_wid,
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i_clk = ClockSignal(),
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i_run = run,
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o_cntr = cntr,
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i_do_loop = do_loop,
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o_finished = finished,
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o_ready = ready,
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i_wform_size = wform_size,
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o_timer = timer,
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i_timer_spacing = timer_spacing,
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o_wb_adr = self.masterbus.adr,
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o_wb_cyc = self.masterbus.cyc,
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o_wb_we = self.masterbus.we,
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o_wb_stb = self.masterbus.stb,
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o_wb_sel = self.masterbus.sel,
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o_wb_dat_w = self.masterbus.dat_w,
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i_wb_dat_r = self.masterbus.dat_r,
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i_wb_ack = self.masterbus.ack,
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)
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def add_ram(self, bus, size):
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self.mmap.regions['ram'].bus = bus
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self.mmap.regions['ram'].size = size
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def add_spi(self, bus):
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# Waveform code has the SPI hardcoded in, because it is a Verilog
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# module.
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self.mmap.regions['spi'].bus = bus
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self.mmap.regions['spi'].size = SPIMaster.width
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def do_finalize(self):
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self.mmap.finalize()
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class SPIMaster(Module):
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# IF THESE ARE CHANGED, CHANGE waveform.v !!
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AD5791_PARAMS = {
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"polarity" :0,
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"phase" :1,
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"spi_cycle_half_wait" : 10,
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"ss_wait" : 5,
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"enable_miso" : 1,
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"enable_mosi" : 1,
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"spi_wid" : 24,
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}
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LT_ADC_PARAMS = {
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"polarity" : 1,
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"phase" : 0,
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"spi_cycle_half_wait" : 5,
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"ss_wait" : 60,
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"enable_mosi" : 0,
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}
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width = 0x20
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public_registers = {
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# The first bit is the "finished" bit, when the master is
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# armed and finished with a transmission.
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# The second bit is the "ready" bit, when the master is
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# not armed and ready to be armed.
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"ready_or_finished": Register(
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origin= 0,
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bitwidth= 2,
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rw=False,
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),
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# One bit to initiate a transmission cycle. Transmission
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# cycles CANNOT be interrupted.
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"arm" : Register(
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origin=4,
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bitwidth=1,
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rw=True,
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),
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# Data sent from the SPI slave.
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"from_slave": Register(
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origin=8,
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bitwidth=32,
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rw=False,
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),
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# Data sent to the SPI slave.
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"to_slave": Register(
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origin=0xC,
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bitwidth=32,
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rw=True
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),
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# Same as ready_or_finished, but halts until ready or finished
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# goes high. Dangerous, might cause cores to hang!
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"wait_ready_or_finished": Register(
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origin=0x10,
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bitwidth=2,
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rw= False,
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),
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}
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def mmio(self, origin):
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r = ""
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for name, reg in self.public_registers.items():
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r += f'{name} = Register(loc={origin + reg.origin},bitwidth={reg.bitwidth},rw={reg.rw}),'
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return r
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""" Wrapper for the SPI master verilog code. """
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def __init__(self, rst, miso, mosi, sck, ss_L,
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polarity = 0,
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phase = 0,
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ss_wait = 1,
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enable_miso = 1,
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enable_mosi = 1,
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spi_wid = 24,
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spi_cycle_half_wait = 1,
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):
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"""
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:param rst: Reset signal.
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:param miso: MISO signal.
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:param mosi: MOSI signal.
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:param sck: SCK signal.
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:param ss: SS signal.
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:param phase: Phase of SPI master. This phase is not the standard
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SPI phase because it is defined in terms of the rising edge, not
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the leading edge. See https://software.mcgoron.com/peter/spi
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:param polarity: See https://software.mcgoron.com/peter/spi.
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:param enable_miso: If ``False``, the module does not read data
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from MISO into a register.
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:param enable_mosi: If ``False``, the module does not write data
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to MOSI from a register.
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:param spi_wid: Verilog parameter: see file.
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:param spi_cycle_half_wait: Verilog parameter: see file.
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"""
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self.bus = Interface(data_width = 32, address_width=32, addressing="byte")
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from_slave = Signal(spi_wid)
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to_slave = Signal(spi_wid)
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finished_or_ready = Signal(2)
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arm = Signal()
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self.comb += [
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self.bus.err.eq(0),
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]
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self.sync += [
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If(self.bus.cyc & self.bus.stb & ~self.bus.ack,
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Case(self.bus.adr[0:5], {
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0x0: [
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self.bus.dat_r[2:].eq(0),
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self.bus.dat_r[0:2].eq(finished_or_ready),
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self.bus.ack.eq(1),
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],
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0x4: [
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If(self.bus.we,
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arm.eq(self.bus.dat_w[0]),
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).Else(
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self.bus.dat_r[1:].eq(0),
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self.bus.dat_r[0].eq(arm),
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),
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self.bus.ack.eq(1),
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],
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0x8: [
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self.bus.dat_r[spi_wid:].eq(0),
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self.bus.dat_r[0:spi_wid].eq(from_slave),
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self.bus.ack.eq(1),
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],
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0xC: [
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If(self.bus.we,
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to_slave.eq(self.bus.dat_r[0:spi_wid]),
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).Else(
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self.bus.dat_r[spi_wid:].eq(0),
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self.bus.dat_r[0:spi_wid].eq(to_slave),
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),
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self.bus.ack.eq(1),
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],
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0x10: If(finished_or_ready[0] | finished_or_ready[1],
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self.bus.dat_r[1:].eq(0),
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self.bus.dat_r.eq(finished_or_ready),
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),
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"default":
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# 0xSPI00SPI
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self.bus.dat_r.eq(0x57100571),
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}),
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).Elif(~self.bus.cyc,
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self.bus.ack.eq(0)
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)
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]
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self.specials += Instance("spi_master_ss",
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p_SS_WAIT = ss_wait,
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p_SS_WAIT_TIMER_LEN = minbits(ss_wait),
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p_CYCLE_HALF_WAIT = spi_cycle_half_wait,
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p_TIMER_LEN = minbits(spi_cycle_half_wait),
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p_WID = spi_wid,
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p_WID_LEN = minbits(spi_wid),
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p_ENABLE_MISO = enable_miso,
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p_ENABLE_MOSI = enable_mosi,
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p_POLARITY = polarity,
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p_PHASE = phase,
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i_clk = ClockSignal(),
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i_rst_L = rst,
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i_miso = miso,
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o_mosi = mosi,
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o_sck_wire = sck,
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o_ss_L = ss_L,
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o_from_slave = from_slave,
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i_to_slave = to_slave,
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o_finished = finished_or_ready[1],
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o_ready_to_arm = finished_or_ready[0],
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i_arm = arm,
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)
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