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Free and open source SoC for Scanning Probe Microscopy
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Peter McGoron 33ec8351d8 correctly (and crudely) simulate control loop 
Issue was that the ADC cycle half wait (SCK delay) was too fast
for the input buffering (since MISO and MOSI are physical inputs
and not FPGA wires).
 		2022-11-24 09:48:19 -05:00
doc fixed fixed point algorithms in python 2022-10-27 17:55:12 -04:00
firmware correctly (and crudely) simulate control loop 2022-11-24 09:48:19 -05:00
software add readme and COPYING 2022-09-17 00:35:47 -04:00
.gitignore update .gitignore 2022-11-17 19:07:49 -05:00
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GUIDELINES.md update GUIDELINES.md 2022-11-17 18:39:48 -05:00
README.md add SPI link 2022-09-17 00:37:42 -04:00

README.md

upsilon

Upsilon is a 100% free and open source STM/AFM controller for FPGAs.

Organization

The project is split into hardware (firmware), kernel (software), and client software (client).

Hardware uses Verilog, LiteX and F4PGA to implement the Soft CPU (Risc-V), hardware communication, PI control loop, image scanning, and tip autoapproach.

Kernel implements the network communication between the hardware and the client software.

The client software receives and interprets data from the hardware.

License

GNU GPL v3.0 or later. Other portions are dual licensed under the CERN OHL-v2-S, or permissive licenses: please view all COPYING files for more legal information.

See also