Peter McGoron 33ec8351d8 correctly (and crudely) simulate control loop ... Issue was that the ADC cycle half wait (SCK delay) was too fast for the input buffering (since MISO and MOSI are physical inputs and not FPGA wires).		2022-11-24 09:48:19 -05:00
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rtl	correctly (and crudely) simulate control loop	2022-11-24 09:48:19 -05:00
A7-constraints.xdc	cleanup	2022-07-12 13:30:28 -04:00
COPYING	clarify licenses	2022-10-27 17:55:57 -04:00
Makefile	Makefiles depend on generated files	2022-07-13 14:11:56 -04:00
generate_csr_locations.py	change CSR types	2022-07-27 09:32:49 -04:00
soc.py	soc.py legal	2022-09-17 00:58:15 -04:00