Peter McGoron 33ec8351d8 correctly (and crudely) simulate control loop ... Issue was that the ADC cycle half wait (SCK delay) was too fast for the input buffering (since MISO and MOSI are physical inputs and not FPGA wires).		2022-11-24 09:48:19 -05:00
..
control_loop	correctly (and crudely) simulate control loop	2022-11-24 09:48:19 -05:00
raster	sketch out raster scan	2022-11-24 00:50:21 -05:00
spi	correctly (and crudely) simulate control loop	2022-11-24 09:48:19 -05:00