upsilon/firmware/rtl/spi
Peter McGoron 33ec8351d8 correctly (and crudely) simulate control loop
Issue was that the ADC cycle half wait (SCK delay) was too fast
for the input buffering (since MISO and MOSI are physical inputs
and not FPGA wires).
2022-11-24 09:48:19 -05:00
..
ramp.v add DAC ramp 2022-11-17 17:32:32 -05:00
spi_master.v import spi v0.2 2022-11-14 08:43:16 -05:00
spi_master_no_read.v add everything im working on 2022-09-16 18:01:34 -04:00
spi_master_no_write.v add verilog SPI 2022-07-21 17:07:52 -04:00
spi_master_ss.v import spi v0.2 2022-11-14 08:43:16 -05:00
spi_master_ss_no_read.v import spi v0.2 2022-11-14 08:43:16 -05:00
spi_master_ss_no_write.v import spi v0.2 2022-11-14 08:43:16 -05:00
spi_master_ss_template.v control loop simulator passes lint 2022-11-21 21:41:50 -05:00
spi_slave.v correctly (and crudely) simulate control loop 2022-11-24 09:48:19 -05:00
spi_slave_no_read.v import spi v0.2 2022-11-14 08:43:16 -05:00
spi_slave_no_write.v some more changes 2022-10-17 00:44:30 -04:00