Makefile
|
reset pins and test clock
|
2023-05-10 14:35:57 -04:00 |
ramp.v
|
add DAC ramp
|
2022-11-17 17:32:32 -05:00 |
spi_master.v
|
reset pins and test clock
|
2023-05-10 14:35:57 -04:00 |
spi_master_no_read.v
|
add everything im working on
|
2022-09-16 18:01:34 -04:00 |
spi_master_no_write.v
|
add verilog SPI
|
2022-07-21 17:07:52 -04:00 |
spi_master_ss.v
|
import spi v0.2
|
2022-11-14 08:43:16 -05:00 |
spi_master_ss_no_read.v
|
import spi v0.2
|
2022-11-14 08:43:16 -05:00 |
spi_master_ss_no_write.v
|
import spi v0.2
|
2022-11-14 08:43:16 -05:00 |
spi_master_ss_template.v
|
reset pins and test clock
|
2023-05-10 14:35:57 -04:00 |
spi_slave.v
|
reset pins and test clock
|
2023-05-10 14:35:57 -04:00 |
spi_slave_no_read.v
|
import spi v0.2
|
2022-11-14 08:43:16 -05:00 |
spi_slave_no_write.v
|
some more changes
|
2022-10-17 00:44:30 -04:00 |
spi_switch.v
|
spi_switch: fix dangling else
|
2023-03-14 15:43:34 +00:00 |
spi_switch_sim.cpp
|
test and simulate spi_switch
|
2023-03-14 15:42:41 +00:00 |