222 lines
7.5 KiB
Python
222 lines
7.5 KiB
Python
# Copyright 2023-2024 (C) Peter McGoron
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#
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# This file is a part of Upsilon, a free and open source software project.
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# For license terms, refer to the files in `doc/copying` in the Upsilon
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# source distribution.
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from migen import *
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from litex.soc.interconnect.wishbone import Interface
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from util import *
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from region import *
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'''
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class Waveform(LiteXModule):
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""" Read from a memory location and output the values in that location
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to a DAC. """
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def __init__(self, max_size=16):
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# Interface used by Waveform to read and write data
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self.bus = Interface(data_width = 32, address_width = 32, addressing="byte")
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# Interface used by Main CPU to control Waveform
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self.mainbus = Interface(data_width = 32, address_width = 32, addressing="byte")
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self.mmap = MemoryMap()
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self.start = Signal()
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self.cntr = Signal(max_size)
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self.loop = Signal()
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self.finished = Signal()
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self.ready = Signal()
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self.comb += [
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If(self.mainbus.cyc & self.mainbus.stb & ~self.mainbus.ack,
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Cases(self.mainbus.adr[0:4], {
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0x0: self.mainbus.dat_r.eq(self.finished << 1 | self.ready),
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0x4: If(self.mainbus.we,
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self.start.eq(self.mainbus.dat_w[0]),
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self.loop.eq(self.mainbus.dat_w[1]),
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).Else(
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self.mainbus.dat_r.eq(self.start << 1 | self.loop),
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),
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0x8: self.mainbus.dat_r.eq(self.cntr)
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}),
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self.mainbus.ack.eq(1),
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).Elif(~self.mainbus.cyc,
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self.mainbus.ack.eq(0),
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),
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]
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'''
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class SPIMaster(Module):
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AD5791_PARAMS = {
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"polarity" :0,
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"phase" :1,
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"spi_cycle_half_wait" : 10,
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"ss_wait" : 5,
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"enable_miso" : 1,
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"enable_mosi" : 1,
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"spi_wid" : 24,
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}
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LT_ADC_PARAMS = {
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"polarity" : 1,
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"phase" : 0,
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"spi_cycle_half_wait" : 5,
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"ss_wait" : 60,
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"enable_mosi" : 0,
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}
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width = 0x20
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public_registers = {
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# The first bit is the "finished" bit, when the master is
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# armed and finished with a transmission.
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# The second bit is the "ready" bit, when the master is
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# not armed and ready to be armed.
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"ready_or_finished": {
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"origin" : 0,
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"width" : 4,
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"rw": False,
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},
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# One bit to initiate a transmission cycle. Transmission
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# cycles CANNOT be interrupted.
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"arm" : {
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"origin": 4,
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"width": 4,
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"rw": True,
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},
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# Data sent from the SPI slave.
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"from_slave": {
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"origin": 8,
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"width": 4,
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"rw": False,
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},
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# Data sent to the SPI slave.
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"to_slave": {
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"origin": 0xC,
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"width": 4,
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"rw": True
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},
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# Same as ready_or_finished, but halts until ready or finished
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# goes high. Dangerous, might cause cores to hang!
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"wait_ready_or_finished": {
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"origin": 0x10,
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"width": 4,
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"rw" : False,
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},
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}
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""" Wrapper for the SPI master verilog code. """
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def __init__(self, rst, miso, mosi, sck, ss_L,
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polarity = 0,
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phase = 0,
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ss_wait = 1,
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enable_miso = 1,
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enable_mosi = 1,
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spi_wid = 24,
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spi_cycle_half_wait = 1,
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):
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"""
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:param rst: Reset signal.
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:param miso: MISO signal.
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:param mosi: MOSI signal.
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:param sck: SCK signal.
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:param ss: SS signal.
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:param phase: Phase of SPI master. This phase is not the standard
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SPI phase because it is defined in terms of the rising edge, not
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the leading edge. See https://software.mcgoron.com/peter/spi
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:param polarity: See https://software.mcgoron.com/peter/spi.
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:param enable_miso: If ``False``, the module does not read data
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from MISO into a register.
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:param enable_mosi: If ``False``, the module does not write data
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to MOSI from a register.
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:param spi_wid: Verilog parameter: see file.
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:param spi_cycle_half_wait: Verilog parameter: see file.
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"""
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self.bus = Interface(data_width = 32, address_width=32, addressing="byte")
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from_slave = Signal(spi_wid)
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to_slave = Signal(spi_wid)
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finished_or_ready = Signal(2)
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arm = Signal()
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self.comb += [
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self.bus.err.eq(0),
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]
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self.sync += [
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If(self.bus.cyc & self.bus.stb & ~self.bus.ack,
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Cases(self.bus.adr[0:5], {
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0x0: [
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self.bus.dat_r[2:].eq(0),
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self.bus.dat_r[0:2].eq(finished_or_ready),
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self.bus.ack.eq(1),
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],
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0x4: [
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If(self.bus.we,
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arm.eq(self.bus.dat_w[0]),
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).Else(
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self.bus.dat_r[1:].eq(0),
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self.bus.dat_r[0].eq(arm),
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),
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self.bus.ack.eq(1),
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]
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0x8: [
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self.bus.dat_r[wid:].eq(0),
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self.bus.dat_r[0:wid].eq(from_slave),
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self.bus.ack.eq(1),
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],
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0xC: [
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If(self.bus.we,
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to_slave.eq(self.bus.dat_r[0:wid]),
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).Else(
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self.bus.dat_r[wid:].eq(0),
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self.bus.dat_r[0:wid].eq(to_slave),
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),
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self.bus.ack.eq(1),
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]
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0x10: If(finished | ready_to_arm,
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self.bus.dat_r[1:].eq(0),
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self.bus.dat_r.eq(finished_or_ready),
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),
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"default":
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# 0xSPI00SPI
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self.bus.dat_r.eq(0x57100571),
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}),
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).Elif(~self.bus.clk,
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self.bus.ack.eq(0)
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)
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]
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self.specials += Instance("spi_master_ss",
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p_SS_WAIT = ss_wait,
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p_SS_WAIT_TIMER_LEN = minbits(ss_wait),
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p_CYCLE_HALF_WAIT = spi_cycle_half_wait,
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p_TIMER_LEN = minbits(spi_cycle_half_wait),
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p_WID = spi_wid,
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p_WID_LEN = minbits(spi_wid),
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p_ENABLE_MISO = enable_miso,
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p_ENABLE_MOSI = enable_mosi,
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p_POLARITY = polarity,
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p_PHASE = phase,
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i_clk = ClockSignal(),
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i_rst_L = rst,
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i_miso = miso,
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o_mosi = mosi,
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o_sck_wire = sck,
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o_ss_L = ss_L,
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o_from_slave = from_slave,
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i_to_slave = to_slave,
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o_finished = finished_or_ready[1],
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o_ready_to_arm = finished_or_ready[0],
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i_arm = arm,
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)
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