Commit Graph

5 Commits

Author SHA1 Message Date
Peter McGoron 1d85e2307d waveform: write and start simulation 2024-03-03 22:35:19 +00:00
Peter McGoron 75d7f298e2 Documentation and register location generation 2024-02-28 13:28:06 +00:00
Peter McGoron da1e9238ab unify region generation and added SPI to PicoRV32 2024-02-27 03:48:22 +00:00
Peter McGoron 88e3d15dd8 Get PicoRV32 to execute code
1. Update LiteX to 2023.12. This update adds wishbone bus addressing
   modes. Before this update, all wishbone buses used word addressing.
   For example, 0x0 mapped to word 0, 0x0 mapped to word 1, etc. This
   caused problems with the PicoRV32 and other modules, which are byte
   addressed.
2. Use adapter to convert between byte and word addressing. The SRAM is
   word addressed. The PicoRV32 shifts the address down by two bits to
   address the correct word. The PicoRV32 core seems to expect this.
3. Add debug register output. This is not working yet.
4. Use LiteX PicoRV32 wishbone adapter instead of PicoRV32 default. This
   seems to be simpler (combinatorial not synchronous).
5. Add some documentation.
6. Seperate config to new config file.
2024-02-25 18:58:34 +00:00
Peter McGoron 3785e3498d reorganize litex code 2024-02-22 15:35:31 +00:00