Peter McGoron 60404cd026 ram_fifo.v: add simulator debugging checks		2022-12-17 10:18:15 -05:00
..
control_loop	control_loop: remove reg keyword, yosys doesnt like it	2022-12-17 09:56:26 -05:00
raster	ram_fifo.v: add simulator debugging checks	2022-12-17 10:18:15 -05:00
spi	correctly (and crudely) simulate control loop	2022-11-24 09:48:19 -05:00