Peter McGoron
67c670cb5c
The PicoRV32 SoC bus generator conflicts with the main SoC bus generator, which causes the address locations in the generated verilog file to be different from the set locations. This code uses custom region classes in soc.py and the Decoder class directly, which is similar to what the finalization of the SoC class uses, and is based on the LiteEth code does. |
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boot | ||
build | ||
buildroot | ||
client | ||
doc | ||
gateware | ||
linux | ||
opensbi/litex/vexriscv | ||
swic | ||
.gitignore | ||
README.md |
README.md
upsilon
Upsilon is a 100% free and open source STM/AFM controller for FPGAs running Linux. Read doc/copying/README.md for license information.
Quickstart
Read doc/docker.md to set up the Docker build environment.
Project Organization
- boot: This folder is the central place for all built files. This includes the kernel image, rootfs, gateware, etc. This directory also includes everything the TFTP server has to access.
- build: Docker build environment.
- buildroot: Buildroot configuration files.
- doc: Documentation.
- doc/copying: Licenses.
- gateware: FPGA source.
- gateware/rtl: Verilog sources.
- gateware/rtl/spi: SPI code (from another repo)
- linux: Software that runs on the controller.
- opensbi: OpenSBI configuration files and source fragments.
- swic: Code that runs on the PicoRV32 soft core.